Power dissipation of the network-on-chip in a system-on-chip for MPEG-4 video encoding

2007 ◽  
Author(s):  
Dragomir Milojevic ◽  
Luc Montperrus ◽  
Diederik Verkest
Keyword(s):  
Power Dissipation ◽  
Network On Chip ◽  
System On Chip ◽  
Video Encoding ◽  
On Chip

Design of Router Supporting Multiply Routing Algorithm for NoC

2014 ◽  
Vol 981 ◽  
pp. 431-434
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Chang Chun Dong ◽  
Lin Hai Cui
Keyword(s):  
Complex System ◽  
High Performance ◽  
Routing Algorithm ◽  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Deterministic Routing ◽  
Key Features ◽  
Design Challenge ◽  
On Chip

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

scholarly journals Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip

2018 ◽  
Vol 67 (12) ◽  
pp. 1818-1834 ◽  
Author(s):  
Weichen Liu ◽  
Lei Yang ◽  
Weiwen Jiang ◽  
Liang Feng ◽  
Nan Guan ◽  
...  
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
Task Mapping ◽  
Dynamically Reconfigurable ◽  
On Chip

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

2013 ◽  
Vol 32 (4) ◽  
pp. 584-596 ◽  
Author(s):  
Yaoyao Ye ◽  
Jiang Xu ◽  
Baihan Huang ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
...  
Keyword(s):  
Optical Network ◽  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
On Chip

scholarly journals Low power network on chip architectures: A survey

2020 ◽  
Vol 2 (3) ◽  
pp. 158-168
Author(s):  
Muhammad Raza Naqvi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Network Architecture ◽  
High Performance ◽  
State Of The Art ◽  
Network On Chip ◽  
System On Chip ◽  
Power Network ◽  
Network Routers ◽  
On Chip

Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

2017 ◽  
Vol 54 ◽  
pp. 60-74 ◽  
Author(s):  
Alireza Monemi ◽  
Jia Wei Tang ◽  
Maurizio Palesi ◽  
Muhammad N. Marsono
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Low Latency ◽  
Core System ◽  
On Chip ◽  
Many Core
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