Design constraint of fine grain supply voltage control LSI

2011 ◽  
Author(s):  
Atsuki Inoue
Keyword(s):  
Supply Voltage ◽  
Voltage Control ◽  
Design Constraint ◽  
Fine Grain

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Voltage Control ◽  
Fault Testing ◽  
Power Supply Voltage ◽  
Delay Fault ◽  
Delay Fault Testing

LOOKUP TABLE-BASED ADAPTIVE BODY BIASING OF MULTIPLE MACROS FOR PROCESS VARIATION COMPENSATION AND LOW LEAKAGE

2010 ◽  
Vol 19 (07) ◽  
pp. 1449-1464 ◽  
Author(s):  
BYUNGHEE CHOI ◽  
YOUNGSOO SHIN
Keyword(s):  
Supply Voltage ◽  
Process Variation ◽  
Power Saving ◽  
Lookup Table ◽  
Low Leakage ◽  
Fine Grain ◽  
Body Biasing ◽  
Block Level ◽  
Adaptive Body Bias ◽  
Body Bias

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.

A 200mV 32b subthreshold processor with adaptive supply voltage control

2012 ◽  
Author(s):  
Sven Luetkemeier ◽  
Thorsten Jungeblut ◽  
Mario Porrmann ◽  
Ulrich Rueckert
Keyword(s):  
Supply Voltage ◽  
Voltage Control

scholarly journals SUPPLY VOLTAGE CONTROL OF HALL SENSORS FOR LOW POWER MAGNETO-ELECTRIC SYSTEMS

2019 ◽  
Vol 2019 (52) ◽  
pp. 62-68
Author(s):  
K. Akynin ◽  
◽  
O. Antonov ◽  
V. Kireiev ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Voltage Control ◽  
Hall Sensors

scholarly journals Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

2019 ◽  
Vol 7 (3) ◽  
pp. 11-18
Author(s):  
Yogesh Kulshethra ◽  
Manish Kule
Keyword(s):  
Leakage Current ◽  
Supply Voltage ◽  
Leakage Power ◽  
Power Gating ◽  
Design Constraint ◽  
Analysis And Design ◽  
Complex Arithmetic ◽  
Look Ahead ◽  
Simulation Results ◽  
Gating Scheme

As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.

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