The analysis of device performance on a different shallow trench isolation (STI) liner scheme

2012 ◽  
Author(s):  
Sun Jong Wang ◽  
Jun Sup Lee ◽  
Sung Hun Kim ◽  
Sung Gun Kang ◽  
Yong-han Roh
Keyword(s):  
Device Performance ◽  
Shallow Trench Isolation ◽  
Trench Isolation

Channel width dependence of mechanical stress effects induced by shallow trench isolation on device performance of nanoscale nMOSFETs

2012 ◽  
Vol 52 (9-10) ◽  
pp. 1949-1952 ◽  
Author(s):  
Seonhaeng Lee ◽  
Dongwoo Kim ◽  
Cheolgyu Kim ◽  
Chiho Lee ◽  
Jeongsoo Park ◽  
...  
Keyword(s):  
Mechanical Stress ◽  
Channel Width ◽  
Device Performance ◽  
Shallow Trench Isolation ◽  
Stress Effects ◽  
Trench Isolation

A Novel Approach to Isolating the Edge of the Shallow Trench Isolation in SiGe HBTs for Improved Device Performance

2014 ◽  
Vol 64 (6) ◽  
pp. 53-63
Author(s):  
R. A. Camillo-Castillo ◽  
Q. Z. Liu ◽  
V. Jain ◽  
J. W. Adkisson ◽  
M. H. Khater ◽  
...  
Keyword(s):  
Device Performance ◽  
Shallow Trench Isolation ◽  
Novel Approach ◽  
Trench Isolation

Shallow Trench Isolation for the 45-nm CMOS Node and Geometry Dependence of STI Stress on CMOS Device Performance

2007 ◽  
Vol 20 (2) ◽  
pp. 59-67 ◽  
Author(s):  
Armin T. Tilke ◽  
Chris Stapelmann ◽  
Manfred Eller ◽  
Karl-Heinz Bach ◽  
Roland Hampp ◽  
...  
Keyword(s):  
Device Performance ◽  
Shallow Trench Isolation ◽  
Geometry Dependence ◽  
Trench Isolation

Characterizing STI CMP Processes with an STI Test Mask Having Realistic Geometric Shapes

2004 ◽  
Vol 816 ◽  
Author(s):  
Xiaolin Xie ◽  
Tae Park ◽  
Duane Boning ◽  
Aaron Smith ◽  
Paul Allard ◽  
...  
Keyword(s):  
Chemical Mechanical Polishing ◽  
Device Performance ◽  
Secondary Effects ◽  
Feature Size ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Oxide Deposition ◽  
Pattern Dependencies ◽  
Small Feature ◽  
Ongoing Development

AbstractChemical mechanical polishing (CMP) has become the enabling planarization method for shallow trench isolation (STI) of sub 0.25μm technology. CMP is able to reduce topography over longer lateral distances than earlier techniques; however, CMP still suffers from pattern dependencies that result in large variation in the post-polish profile across a chip. In the STI process, insufficient polish will leave residue nitride and cause device failure, while excess dishing and erosion degrade device performance.Our group has proposed several chip-scale CMP pattern density models [1], and a methodology using designed dielectric CMP test mask to characterize CMP processes [2]. The methodology has proven helpful in understanding STI CMP; however, it has several limitations as the existing test mask primarily consists of arrays of lines and spaces of large feature size varying from 10 to 100 μm. In this paper, we present a new STI characterization mask, which consists of various rectangular, L-shape, and X-shape structures of feature sizes down to submicron. The mask is designed to study advanced STI CMP processes better, as it is more representative of real STI structures. The small feature size amplifies the effects of edge acceleration and oxide deposition bias, and thus enables us to study their impact better. Experimental data from an STI CMP process is shown to verify the methodology, and these secondary effects are explored. The new mask and data guide ongoing development of improved pattern dependent STI CMP models.

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Advances in Chemical-Mechanical Planarization

MRS Bulletin ◽  
2002 ◽  
Vol 27 (10) ◽  
pp. 743-751 ◽  
Author(s):  
Rajiv K. Singh ◽  
Rajeev Bajaj
Keyword(s):  
Surface Topography ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Chemical Mechanical Planarization ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Fundamental Understanding ◽  
Copper Polishing ◽  
Future Growth

AbstractThe primary aim of this issue of MRS Bulletin is to present an overview of the materials issues in chemical–mechanical planarization (CMP), also known as chemical–mechanial polishing, a process that is used in the semiconductor industry to isolate and connect individual transistors on a chip. The CMP process has been the fastest-growing semiconductor operation in the last decade, and its future growth is being fueled by the introduction of copper-based interconnects in advanced microprocessors and other devices. Articles in this issue range from providing a fundamental understanding of the CMP process to the latest advancements in the field. Topics covered in these articles include an overview of CMP, fundamental principles of slurry design, understanding wafer–pad–slurry interactions, process integration issues, the formulation of abrasive-free slurries for copper polishing, understanding surface topography issues in shallow trench isolation, and emerging applications.

Analysis of Self-Heating Effects on vertical FET according to Shallow Trench Isolation

2017 ◽  
Vol 137 ◽  
pp. 123-127
Author(s):  
Ilho Myeong ◽  
Dokyun Son ◽  
Hyunsuk Kim ◽  
Myounggon Kang ◽  
Hyungcheol Shin
Keyword(s):  
Shallow Trench Isolation ◽  
Self Heating ◽  
Heating Effects ◽  
Trench Isolation
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