Instruction Set Customization of Application Speci.c Processors for Network Processing: A Case Study

2006 ◽  
Author(s):  
M.M. Rahman Mozumdar ◽  
K. Karuri ◽  
A. Chattopadhyay ◽  
S. Kraemer ◽  
H. Scharwaechter ◽  
...  
Keyword(s):  
Instruction Set ◽  
Network Processing

scholarly journals Hardware Acceleration for RLNC: A Case Study Based on the Xtensa Processor with the Tensilica Instruction-Set Extension

Electronics ◽  
2018 ◽  
Vol 7 (9) ◽  
pp. 180 ◽  
Author(s):  
Javier Acevedo ◽  
Robert Scheffel ◽  
Simon Wunderlich ◽  
Mattis Hasler ◽  
Sreekrishna Pandi ◽  
...  
Keyword(s):  
Hardware Acceleration ◽  
Code Word ◽  
Instruction Set ◽  
Linear Network ◽  
Galois Fields ◽  
Linear Network Coding ◽  
Multiple Data ◽  
Instruction Set Extension ◽  
Energy Constrained

Random linear network coding (RLNC) can greatly aid data transmission in lossy wireless networks. However, RLNC requires computationally complex matrix multiplications and inversions in finite fields (Galois fields). These computations are highly demanding for energy-constrained mobile devices. The presented case study evaluates hardware acceleration strategies for RLNC in the context of the Tensilica Xtensa LX5 processor with the tensilica instruction set extension (TIE). More specifically, we develop TIEs for multiply-accumulate (MAC) operations for accelerating matrix multiplications in Galois fields, single instruction multiple data (SIMD) instructions operating on consecutive memory locations, as well as the flexible-length instruction extension (FLIX). We evaluate the number of clock cycles required for RLNC encoding and decoding without and with the MAC, SIMD, and FLIX acceleration strategies. We also evaluate the RLNC encoding and decoding throughput and energy consumption for a range of RLNC generation and code word sizes. We find that for GF ( 2 8 ) and GF ( 2 16 ) RLNC encoding, the SIMD and FLIX acceleration strategies achieve speedups of approximately four hundred fold compared to a benchmark C code implementation without TIE. We also find that the unicore Xtensa LX5 with SIMD has seven to thirty times higher RLNC encoding and decoding throughput than the state-of-the-art ODROID XU3 system-on-a-chip (SoC) operating with a single core; the Xtensa LX5 with FLIX, in turn, increases the throughput by roughly 25% compared to utilizing only SIMD. Furthermore, the Xtensa LX5 with FLIX consumes roughly four orders of magnitude less energy than the ODROID XU3 SoC.

scholarly journals A Hybrid NoC-Based MPSoC Simulator

2012 ◽  
Vol 6-7 ◽  
pp. 238-242
Author(s):  
Lin Xiang Shi ◽  
Zhe Zhang
Keyword(s):  
Network On Chip ◽  
Traffic Model ◽  
Instruction Set ◽  
Accurate Model ◽  
Level Model ◽  
On Chip ◽  
Simulation And Evaluation ◽  
Core Simulation ◽  
And Behavior

A hybrid MPSoC (Multi-Processor SoC) simulator was proposed in this paper. The simulator provides statistical traffic model and behavior-level model for computation, along with cycle-accurate model on basis of ISS (Instruction-Set Simulator) including ARM and TI DSP. The simulator also provides NoC (Network-on-Chip) and traditional bus for on-chip communication and interconnection. As shown in the case study, the proposed simulator may improve the efficiency of building-up a multi-core simulation platform, and then may be used for simulation and evaluation of the constructed multi-core and NoC architectures.

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