Low noise, low power dissipation mHEMT-based amplifiers for phased array application

2010 ◽  
Author(s):  
Paul Blount ◽  
Charles J Trantanell ◽  
Louis Coryell ◽  
Raymond Lau
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Phased Array ◽  
Low Noise ◽  
Low Power Dissipation

Characterization of lateral bipolar transistor structures

1990 ◽  
Vol 48 (4) ◽  
pp. 628-629
Author(s):  
N. David Theodore ◽  
Sophie Verdonckt-Vandebroek ◽  
C. Barry Carter ◽  
S. Simon Wong
Keyword(s):  
Low Power ◽  
Cross Sections ◽  
Power Dissipation ◽  
Diagnostic Techniques ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Structural Defects ◽  
Low Power Dissipation ◽  
Packing Densities ◽  
Driving Capability

Semiconductor devices are being scaled down into the submicron regime in order to meet technological demands for increased device-packing densities. Other factors considered for device design include low power dissipation, noise immunity, speed and high driving capability. Of these factors, high packing densities and low power dissipation can be derived using Coinplementary-Metal-Oxide-Semiconductor (CMOS) schemes. Bipolar-Junction-Transistor (BJT) schemes on the other hand provide driving capability, low noise performance and speed, at the expense however of greater device power- consumption. Combining CMOS and BJT technologies, a compromise can be struck between devicespeed and power dissipation. Most such combinations have resulted in vertical BJT requiring complex fabrication sequences. Recently, simpler lateral BJTs have been proposed for use in Bipolar CMOS processes. The viability of such semiconducting devices depends in part on the absence or controlled presence of structural defects. Diagnostic techniques are therefore required that are capable of high spatial resolution, for investigating the origin, behavior and possible elimination of fabrication-process-induced defects. Transmission electron microscopy (TEM) of device cross-sections can be effectively used for this purpose. In this study, lateral BJT structures are characterized using cross-section TEM and the results are correlated with electrical device-behavior.

scholarly journals Development of Low-Noise Small-Area 24 GHz CMOS Radar Sensor

2016 ◽  
Vol 2016 ◽  
pp. 1-12
Author(s):  
Min Yoon ◽  
Jee-Youl Ryu
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Small Area ◽  
Noise Figure ◽  
Low Noise ◽  
Cmos Process ◽  
Radar Sensor ◽  
Low Power Dissipation ◽  
Chip Size ◽  
24 Ghz

We present a low-noise small-area 24 GHz CMOS radar sensor for automotive collision avoidance. This sensor is based on direct-conversion pulsed-radar architecture. The proposed circuit is implemented using TSMC 0.13 μm RF (radio frequency) CMOS (fT/fmax=120/140 GHz) technology, and it is powered by a 1.5 V supply. This circuit uses transmission lines to reduce total chip size instead of real bulky inductors for input and output impedance matching. The layout techniques for RF are used to reduce parasitic capacitance at the band of 24 GHz. The proposed sensor has low cost and low power dissipation since it is realized using CMOS process. The proposed sensor showed the lowest noise figure of 2.9 dB and the highest conversion gain of 40.2 dB as compared to recently reported research results. It also showed small chip size of 0.56 mm2, low power dissipation of 39.5 mW, and wide operating temperature range of −40 to +125°C.

Low-Noise, Low Power Dissipation GaAs Monolithic Broad-Band Amplifiers

1983 ◽  
Vol 31 (5) ◽  
pp. 412-417 ◽  
Author(s):  
K. Honjo ◽  
T. Sugiura ◽  
T. Tsuji ◽  
T. Ozawa
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Broad Band ◽  
Low Noise ◽  
Low Power Dissipation

Low Power dissipation of Ring Counter using Dual sleep Transistor approach

2014 ◽  
Vol 4 (3) ◽  
pp. 9-13
Author(s):  
M. Balaji ◽  
◽  
B. Keerthana ◽  
K. Varun ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Ring Counter ◽  
Low Power Dissipation
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