A unidirectional bit serial systolic architecture for double-basis division over GF(2/sup m/)

2004 ◽  
Author(s):  
A.K. Daneshbeh ◽  
M.A. Hasan
Keyword(s):  
Systolic Architecture ◽  
Bit Serial

scholarly journals Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier

2012 ◽  
pp. 61-67
Author(s):  
M.N. Murty ◽  
S.S. Nayak ◽  
Binayak Padhy ◽  
S.N. Panda
Keyword(s):  
Image Processing ◽  
Computational Time ◽  
Partial Product ◽  
Real Time Systems ◽  
Arithmetic Operations ◽  
Systolic Architecture ◽  
Parallel Multiplier ◽  
Discrete Orthogonal ◽  
Time Systems ◽  
Bit Serial

Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with small computational time. In this paper, a 4-bit serial - parallel multiplier, which can perform both positive and negative multiplications, is presented. Baugh-Wooley algorithm necessitates complementation of last bit of each partial product except the last partial product in which all but the last bit are complemented. In the proposed algorithm all bits of the last partial product are complemented. This modification results in considerable reduction in hardware compared to Baugh-Wooley multiplier. This multiplier can be used for implementation of discrete orthogonal transforms, which are used in many applications, including image and signal processing. This paper presents a 2D bit-level systolic architecture for a matrixmatrix multiplier. A comparison with similar structures has shown that the proposed structure performs better.

Division and bit-serial multiplication over GF(qm)

1992 ◽  
Vol 139 (3) ◽  
pp. 230 ◽  
Author(s):  
M.A. Hasan ◽  
V.K. Bhargava
Keyword(s):  
Bit Serial

scholarly journals Six shades lighter: a bit-serial implementation of the AES family

2021 ◽  
Author(s):  
Sergio Roldán Lombardía ◽  
Fatih Balli ◽  
Subhadeep Banik
Keyword(s):  
Block Cipher ◽  
Block Ciphers ◽  
Authenticated Encryption ◽  
Current Standard ◽  
Asic Circuit ◽  
The Family ◽  
Encryption And Decryption ◽  
Preliminary Version ◽  
Reduction In Area ◽  
Bit Serial

AbstractRecently, cryptographic literature has seen new block cipher designs such as , or that aim to be more lightweight than the current standard, i.e., . Even though family of block ciphers were designed two decades ago, they still remain as the de facto encryption standard, with being the most widely deployed variant. In this work, we revisit the combined one-in-all implementation of the family, namely both encryption and decryption of each as a single ASIC circuit. A preliminary version appeared in Africacrypt 2019 by Balli and Banik, where the authors design a byte-serial circuit with such functionality. We improve on their work by reducing the size of the compact circuit to 2268 GE through 1-bit-serial implementation, which achieves 38% reduction in area. We also report stand-alone bit-serial versions of the circuit, targeting only a subset of modes and versions, e.g., and . Our results imply that, in terms of area, and can easily compete with the larger members of recently designed family, e.g., , . Thus, our implementations can be used interchangeably inside authenticated encryption candidates such as , or in place of .

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