scholarly journals A temporal logic for input output symbolic transition systems

2005 ◽  
Author(s):  
M. Aiguier ◽  
C. Gaston ◽  
P. Le Gall ◽  
D. Longuet ◽  
A. Touil
Keyword(s):  
Temporal Logic ◽  
Input Output ◽  
Transition Systems ◽  
Symbolic Transition Systems

Symbolic-Based Monitoring for Embedded Applications

2015 ◽  
pp. 939-961
Author(s):  
Pramila Mouttappa ◽  
Stephane Maag ◽  
Ana Cavalli
Keyword(s):  
System Design ◽  
Research Community ◽  
Input Output ◽  
Transition Systems ◽  
Execution Traces ◽  
Novel Approach ◽  
Security Properties ◽  
Symbolic Transition Systems ◽  
And Control ◽  
Embedded Applications

Testing embedded systems to find errors and to validate that the implemented system as per the specifications and requirements has become an important part of the system design. The research community has proposed several formal approaches these last years, but most of them only consider the control portion of the protocol, neglecting the data portions, or are confronted with an overloaded amount of data values to consider. In this chapter, the authors present a novel approach to model protocol properties of embedded application in terms of Input-Output Symbolic Transition Systems (IOSTS) and show how they can be tested on real execution traces taking into account the data and control portions. These properties can be designed to test the conformance of a protocol as well as security aspects. A parametric trace slicing approach is presented to match trace and property. This chapter is illustrated by an application to a set of real execution traces extracted from a real automotive Bluetooth framework with functional and security properties.

Symbolic-Based Monitoring for Embedded Applications

2014 ◽  
pp. 52-74
Author(s):  
Pramila Mouttappa ◽  
Stephane Maag ◽  
Ana Cavalli
Keyword(s):  
System Design ◽  
Research Community ◽  
Input Output ◽  
Transition Systems ◽  
Execution Traces ◽  
Novel Approach ◽  
Security Properties ◽  
Symbolic Transition Systems ◽  
And Control ◽  
Embedded Applications

Testing embedded systems to find errors and to validate that the implemented system as per the specifications and requirements has become an important part of the system design. The research community has proposed several formal approaches these last years, but most of them only consider the control portion of the protocol, neglecting the data portions, or are confronted with an overloaded amount of data values to consider. In this chapter, the authors present a novel approach to model protocol properties of embedded application in terms of Input-Output Symbolic Transition Systems (IOSTS) and show how they can be tested on real execution traces taking into account the data and control portions. These properties can be designed to test the conformance of a protocol as well as security aspects. A parametric trace slicing approach is presented to match trace and property. This chapter is illustrated by an application to a set of real execution traces extracted from a real automotive Bluetooth framework with functional and security properties.

Revisiting Compatibility of Input-Output Modal Transition Systems

2014 ◽  
pp. 367-381 ◽  
Author(s):  
Ivo Krka ◽  
Nicolás D’Ippolito ◽  
Nenad Medvidović ◽  
Sebastián Uchitel
Keyword(s):  
Input Output ◽  
Transition Systems ◽  
Modal Transition Systems

Automatic verification of sequential circuit designs

1992 ◽  
Vol 339 (1652) ◽  
pp. 105-120 ◽  
Keyword(s):  
Temporal Logic ◽  
State Transition ◽  
Logic Model ◽  
Decision Diagrams ◽  
Sequential Circuit ◽  
Transition Systems ◽  
Binary Decision ◽  
The Past ◽  
State Transition System ◽  
Logic Model Checking

Temporal logic model checking is a method for automatically deciding if a sequential circuit satisfies its specifications. In this approach, the circuit is modelled as a state transition system, and specifications are given by temporal logic formulas. Efficient search algorithms are used to determine if the specifications are satisfied or not. The procedure has been used successfully in the past to find subtle errors in a number of non trivial circuit designs. Recently, the size of the circuits that can be handled by this technique has increased dramatically. It is now possible to verify transition systems that are many orders of magnitude larger than was previously the case. In this paper, we describe some of the techniques that have made this increase possible. These techniques are based on the use of binary decision diagrams to represent transition systems and sets of states.

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