Wireless performance improvement using an embedded balanced dipole antenna in laptop computer considering platform noise impact

2008 ◽  
Author(s):  
Seong-Youp Suh ◽  
V.K. Nair ◽  
A. Konanur ◽  
U. Karacaoglu ◽  
Kwan-ho Lee
Keyword(s):  
Performance Improvement ◽  
Dipole Antenna ◽  
Laptop Computer ◽  
Noise Impact

scholarly journals Performance Improvement of a Direction Finding System Antenna Using Method of Moment (MOM)

2020 ◽  
Vol 5 (1) ◽  
pp. 27-32
Author(s):  
Ogonna F. Anaebo ◽  
Gloria N. Ezeh ◽  
Onyebuchi Chikezie Nosiri ◽  
Cosmas K. Agubor
Keyword(s):  
Performance Improvement ◽  
Vector Potential ◽  
Software Tool ◽  
Direction Finding ◽  
Dipole Antenna ◽  
False Alarms ◽  
Magnetic Vector Potential ◽  
Method Of Moment ◽  
Magnetic Vector ◽  
Yagi Antenna

This paper focuses on the Performance Improvement of a Direction Finding System Antenna Using Method of Moment (MoM) Approach. The work is developed to provide an approximate current distribution for a direction finding system antenna by employing the use of Method of Moment on an array of Yagi-uda antenna. The parameters of the experimental antenna are derived and analyzed via Magnetic Vector Potential (MVP) operator. The accurate current flowing through the radiating elements of the direction finding system is analyzed using combination of Method of Moment technique and Magnetic Vector Potential (MVP) operator. This helps to avoid the detection of false alarms and inability of the system to detect remote targets. A typical direction finding system Yagi antenna is designed and operated at a frequency range of 0.6- 0.8 GHz. The antenna has a single reflector, an active (driven) element and three (3) parasitic directors. The antenna parameters are simulated using MatLab R2010a software tool. The average pointing vector of the designed Yagi antenna was obtained as 3.73watt per square metre, and Radiation Intensity value of about 9.400 coulomb per kilogram. The simulation results indicate an appreciable increase in directivity of 9.03dBi, an enhanced directive gain compared to that of the equivalent dipole antenna of 1.76dBi, signifying 7.27dBi enhancement.

Dual-/Triple-Band Asymmetric Dipole Antenna for WLAN Operation in Laptop Computer

2013 ◽  
Vol 61 (7) ◽  
pp. 3808-3813 ◽  
Author(s):  
Chow-Yen-Desmond Sim ◽  
Hsuan-Yu Chien ◽  
Ching-Her Lee
Keyword(s):  
Dipole Antenna ◽  
Laptop Computer ◽  
Triple Band

Peningkatan kinerja guru dalam pembelajaran di kelas melalui supervisi edukatif Kolaboratif secara periodik MIS Lawe kongker Tahun pelajaran 2019/2020

2020 ◽  
Vol 1 (3) ◽  
pp. 316-324
Author(s):  
Syukrani Kadir
Keyword(s):  
Student Learning ◽  
Performance Improvement ◽  
Teacher Performance ◽  
Learning Cycle ◽  
Learning Achievement ◽  
Educational Supervision ◽  
Average Action ◽  
Learning Plans

periodically in preparing learning plans, implementing learning, assessing learning achievement, carrying out follow-up assessments of student learning achievement that can improve teacher performance. This performance improvement is through periodic collaborative educational supervision. Based on the results of educational supervision in cycle I and cycle II, teacher performance increased, namely in cycle I, teacher performance in preparing learning plans in cycle I reached 71.98%, while cycle II was 92.44%. Teacher performance in implementing learning cycle I reached 72.44% while cycle II reached 93.81%. Teacher performance in assessing learning achievement in cycle Im reached 81.30% while cycle II was 90.56%. Teacher performance in carrying out follow-up assessments of student learning achievement in the first cycle reached 59.76% while the second cycle was 83.00%. Thus, the average action cycle II was above 75.00%. Based on the results of this study, it can be concluded that the teacher's performance has increased in preparing learning plans, implementing learning, assessing learning achievement, carrying out follow-up assessments of student learning achievement.

PROTOTYPE ALAT PEMANTAU SALURAN AIR BAWAH TANAH DENGAN MENGGUNAKAN WEBCAM C170 BERBASIS RASPBERRY PI

2015 ◽  
Vol 1 (1) ◽  
pp. 37-45
Author(s):  
Irwansyah Irwansyah ◽  
Hendra Kusumah ◽  
Muhammad Syarif
Keyword(s):  
Real Time ◽  
Monitoring System ◽  
Public Awareness ◽  
Underground Water ◽  
Raspberry Pi ◽  
Laptop Computer ◽  
Web Browser ◽  
Disaster Monitoring ◽  
The Times ◽  
Human Desire

Along with the times, recently there have been found tool to facilitate human’s work. Electronics is one of technology to facilitate human’s work. One of human desire is being safe, so that people think to make a tool which can monitor the surrounding condition without being monitored with people’s own eyes. Public awareness of the underground water channels currently felt still very little so frequent floods. To avoid the flood disaster monitoring needs to be done to underground water channels.This tool is controlled via a web browser. for the components used in this monitoring system is the Raspberry Pi technology where the system can take pictures in real time with the help of Logitech C170 webcam camera. web browser and Raspberry Pi make everyone can control the devices around with using smartphone, laptop, computer and ipad. This research is expected to be able to help the users in knowing the blockage on water flow and monitored around in realtime.

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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