Analysis of on-chip antennas for high-speed signal transmission in silicon integrated circuits

2008 ◽  
Author(s):  
K. Kimoto ◽  
N. Sasaki ◽  
S. Kubota ◽  
W. Moriyama ◽  
T. Kikkawa
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Signal Transmission ◽  
Silicon Integrated Circuits ◽  
On Chip

Electro‐optic sampling of high‐speed silicon integrated circuits using a GaAs probe tip

1991 ◽  
Vol 59 (2) ◽  
pp. 146-148 ◽  
Author(s):  
Michael S. Heutmaker ◽  
George T. Harvey ◽  
Philip F. Bechtold
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Electro Optic ◽  
Silicon Integrated Circuits

Bipolar device technology challenge and opportunity

1985 ◽  
Vol 63 (6) ◽  
pp. 683-692 ◽  
Author(s):  
H. D. Barber
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Chemical Vapor ◽  
Low Noise ◽  
Isolation Techniques ◽  
Propagation Delays ◽  
Technological Barriers ◽  
On Chip ◽  
Bipolar Device

Silicon bipolar device technologies provided 65% of the world's integrated circuits in 1983. Where low noise, high current, low or high voltage, high speed or low cost are required, bipolar technologies are used. This paper will review the present status of bipolar device technologies, which make possible 100-ps gate-propagation delays, 150-μm2 gate areas, 1-GHz bandwidth amplifiers, on-chip control of over 1-A, 350-V operation, 14-GHz fT's and 10-ns. analogue-to-8-bit digital conversion. These devices are realized because of advances in isolation techniques, chemical-vapor deposition, photolithography, diffusion, ion implantation, conductor–contact interconnection technology, etching processes, and materials preparation. This paper will discuss some of the fundamental problems, modelling difficulties, and technological barriers that will impact the future development of bipolar integrated circuits.

scholarly journals Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 964
Author(s):  
Namra Akram ◽  
Mehboob Alam ◽  
Rashida Hussain ◽  
Asghar Ali ◽  
Shah Muhammad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Order Reduction ◽  
High Speed ◽  
Order Reduction ◽  
Reliable Operation ◽  
Model Order ◽  
Reduced Order ◽  
Reduction Methods ◽  
On Chip

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

Integrated on-chip antennas for communication on and between monolithic integrated circuits

2009 ◽  
Vol 1 (4) ◽  
pp. 309-314 ◽  
Author(s):  
Hristomir Yordanov ◽  
Peter Russer
Keyword(s):  
Integrated Circuits ◽  
Transmission Line ◽  
Cross Talk ◽  
Electronic Circuit ◽  
Signal Transmission ◽  
Chip Area ◽  
Integrated Antennas ◽  
Monolithic Integrated Circuits ◽  
The Cross ◽  
On Chip

The rate of signal transmission on or between monolithic integrated circuits is limited by the cross-talk and the dispersion due to the wired interconnects. The bandwidth limitations can be overcome by wireless chip-to-chip and on-chip interconnects via integrated antennas. In this work the utilization of the electronic circuit ground planes as radiating elements for the integrated antennas has been proposed. This allows for optimal usage of chip area, as the antennas share the same metallization structure as the circuits. By exciting the interconnects between the patch areas in transmission line modes as well as in antenna modes, the interference between signals from circuit to circuit and antenna excitation signals is minimized. This has been achieved by inserting a transformer in the antenna feeding network. Examples of possible antenna and feeding structures have been investigated numerically. Scaled prototypes of the integrated antennas have been manufactured and measured.

scholarly journals Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits

1992 ◽  
Vol 14 (4) ◽  
pp. 199-218 ◽  
Author(s):  
K. Z. Dimopoulos ◽  
J. N. Avaritsiotis ◽  
S. J. White
Keyword(s):  
Integrated Circuits ◽  
Transmission Lines ◽  
High Speed ◽  
Pulse Propagation ◽  
Unit Length ◽  
Coupled Line ◽  
Lossy Transmission ◽  
Electrical Modelling ◽  
High Bit Rates ◽  
On Chip

A method for the electrical parameters analysis and modelling of lossy-coupled multilayer on-chip interconnection lines at high bit rates is presented in detail. It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to simulate the pulse propagation characteristics in high-speed integrated circuits. First the capacitance, inductance, conductance and resistance matrices per unit length for the given multiconductor geometry is computed. A multiple coupled line model consisting of uncoupled lossy transmission lines and linear dependent current and voltage sources if finally calculated according to the capacitance, inductance, conductance and resistance matrix values computed.

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