scholarly journals Body-bootstrapped-buffer circuit for CMOS static power reduction

2008 ◽  
Author(s):  
Liang-Yu Loy ◽  
Weijia Zhang ◽  
Zhi-Hui Kong ◽  
Wang-Ling Goh ◽  
Kiat-Seng Yeo
Keyword(s):  
Power Reduction ◽  
Static Power

scholarly journals An Efficient Power Optimized 32 bit BCD Adder Using Multi-Channel Technique

2017 ◽  
Vol 6 (02) ◽  
pp. 07-12
Author(s):  
Diksha Siddhamshittiwar
Keyword(s):  
Average Power ◽  
Full Adder ◽  
Deep Submicron ◽  
Power Reduction ◽  
Vlsi Circuits ◽  
Power Gating ◽  
Static Power ◽  
Simulation Results ◽  
Efficient Power ◽  
Standby Mode

Static power reduction is a challenge in deep submicron VLSI circuits. In this paper 28T full adder circuit, 14T full adder circuit and 32 bit power gated BCD adder using the full adders respectively were designed and their average power was compared. In existing work a conventional full adder is designed using 28T and the same is used to design 32 bit BCD adder. In the proposed architecture 14T transmission gate based power gated full adder is used for the design of 32 bit BCD adder. The leakage supremacy dissipated during standby mode in all deep submicron CMOS devices is reduced using efficient power gating and multi-channel technique. Simulation results were obtained using Tanner EDA and TSMC_180nm library file is used for the design of 28T full adder, 14T full adder and power gated BCD adder and a significant power reduction is achieved in the proposed architecture.

Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches

2014 ◽  
Vol 22 (1) ◽  
pp. 13-26 ◽  
Author(s):  
Zhaobo Zhang ◽  
Xrysovalantis Kavousianos ◽  
Krishnendu Chakrabarty ◽  
Yiorgos Tsiatouhas
Keyword(s):  
Power Reduction ◽  
Power Switches ◽  
Static Power ◽  
Multi Mode

scholarly journals An Optimization Mechanism Intended for Static Power Reduction Using Dual-Technique

2012 ◽  
Vol 2012 ◽  
pp. 1-12
Author(s):  
Rodolfo P. Santos ◽  
Gabriela S. Clemente ◽  
Abel Silva-Filho ◽  
Cristiano Araújo ◽  
Adriano Sarmento ◽  
...  
Keyword(s):  
Power Reduction ◽  
Design Flow ◽  
Integrated Systems ◽  
Circuit Modeling ◽  
Cell Replacement ◽  
Consumption Reduction ◽  
Static Power ◽  
A Cell ◽  
Optimization Mechanism ◽  
Threshold Technique

Power consumption reduction is a challenge nowadays. Techniques for dynamic and static power minimization have been proposed, but most of them are very time consuming. This work proposes an algorithm for reducing static power, which can be perfectly inserted in the conventional design flow for integrated systems considering an open source environment (open accessinfrastructure). The proposed approach, based on a Dual-Threshold technique, replaces part of the cells of the circuit by cells with a higher threshold voltage without resulting in timing violations in the circuit. The decision to replace a cell is based on timing estimates of the circuit modeling with the cell replacement, before it is actually replaced. The fact that only some cells are replaced every iteration results in a reduction of the runtime of the algorithm. Additionally, results showed a reduction in static power up to 39.28%, when applying the proposed approach in the ISCAS85 benchmark circuits.

scholarly journals DFT and Minimum Leakage Pattern Generation for Static Power Reduction During Test and Burn-In

2010 ◽  
Vol 18 (3) ◽  
pp. 392-400 ◽  
Author(s):  
Wei-Chung Kao ◽  
Wei-Shun Chuang ◽  
Hsiu-Ting Lin ◽  
James Chien-Mo Li ◽  
Vasco Manquinho
Keyword(s):  
Power Reduction ◽  
Pattern Generation ◽  
Static Power

scholarly journals SIGNAL-PATH-LEVEL DUAL-Vt ASSIGNMENT FOR LEAKAGE POWER REDUCTION

2006 ◽  
Vol 15 (02) ◽  
pp. 197-216 ◽  
Author(s):  
YU WANG ◽  
HUAZHONG YANG ◽  
HUI WANG
Keyword(s):  
Threshold Voltage ◽  
High Performance ◽  
Low Voltage ◽  
Power Reduction ◽  
Threshold Voltages ◽  
Fast Development ◽  
Static Power ◽  
Signal Path ◽  
Subcircuit Extraction ◽  
New Algorithms

Along with the fast development of dual-threshold voltage (dual-Vt) and multi-threshold technology, it is possible to use them to reduce static power in low-voltage high-performance circuits. In this paper, we propose a new method to realize CMOS digital circuits that are implemented with dual-Vt technology. We first present a new signal-path-level circuit model which effectively deals with the fact that there can be two threshold voltages assigned to a single gate. In order to assign proper threshold voltage to all the signal-paths in the circuit, our new algorithms introduce the concept of subcircuit extraction and include the hierarchy algorithms which are effective and fast. Experimental results show that our algorithms produce a significant reduction for the ISCAS85 benchmark circuits.

A Novel Compiler Assisted Approach for Issue Queue Power Reduction

2014 ◽  
Vol 543-547 ◽  
pp. 1981-1986
Author(s):  
Peng Wei Lv ◽  
Jian Qing Xiao ◽  
Sen Mao Shi
Keyword(s):  
Energy Consumption ◽  
Power Dissipation ◽  
Power Reduction ◽  
Instruction Level Parallelism ◽  
Superscalar Processors ◽  
Control Logic ◽  
Complex Control ◽  
Compiler Analysis ◽  
Static Power ◽  
Level Parallelism

Superscalar processors contain complex control logic in order to extract sufficient instruction level parallelism (ILP). The issue logic is one of the main sources of power dissipation in current superscalar processors. It has been estimated that up to 30% of the energy consumed by a processor is in the issue logic. This paper presents a novel compiler assisted approach to power reduction where we use compiler analysis to pass information to the processor about the number of entries needed, allowing the processor to resize the issue queue dynamically which limit the number of instruction dispatched and resident in the queue reduces the energy consumption without adversely affecting performance. Compared with hardware scheme, our approach is simpler faster and saves more energy. Using the approach we achieve 43.3% dynamic and 28.5% static power savings.

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