High Level Synthesis with Multiple supply Voltages for Energy and Combined Peak Power Minimization

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems ◽

10.1109/apccas.2006.342178 ◽

2006 ◽

Author(s):

Zhen Zhao ◽

Jinian Bian ◽

Zhipeng Liu ◽

Yunfeng Wang ◽

Kang Zhao

Keyword(s):

Peak Power ◽

High Level Synthesis ◽

Power Minimization ◽

Supply Voltages ◽

High Level ◽

Multiple Supply Voltages

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Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply Voltages

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e96.a.2597 ◽

2013 ◽

Vol E96.A (12) ◽

pp. 2597-2611 ◽

Cited By ~ 2

Author(s):

Shin-ya ABE ◽

Youhua SHI ◽

Kimiyoshi USAMI ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Supply Voltages ◽

High Level ◽

Multiple Supply Voltages

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MH4 : multiple-supply-voltages aware high-level synthesis for high-integrated and high-frequency circuits for HDR architectures

IEICE Electronics Express ◽

10.1587/elex.9.1414 ◽

2012 ◽

Vol 9 (17) ◽

pp. 1414-1422 ◽

Cited By ~ 14

Author(s):

Shin-ya Abe ◽

Youhua Shi ◽

Masao Yanagisawa ◽

Nozomu Togawa

Keyword(s):

High Frequency ◽

High Level Synthesis ◽

Supply Voltages ◽

High Level ◽

Multiple Supply Voltages

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High level synthesis for peak power minimization using ILP

Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors ◽

10.1109/asap.2000.862382 ◽

2002 ◽

Cited By ~ 10

Author(s):

Wen-Tsong Shiue

Keyword(s):

Peak Power ◽

High Level Synthesis ◽

Power Minimization ◽

High Level

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An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages

2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT) ◽

10.1109/vldi-dat.2013.6533808 ◽

2013 ◽

Author(s):

S. Abe ◽

Youhua Shi ◽

K. Usami ◽

M. Yanagisawa ◽

N. Togawa

Keyword(s):

Energy Efficient ◽

High Level Synthesis ◽

Synthesis Algorithm ◽

Supply Voltages ◽

High Level ◽

Multiple Supply Voltages

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Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology

2007 Canadian Conference on Electrical and Computer Engineering ◽

10.1109/ccece.2007.418 ◽

2007 ◽

Cited By ~ 2

Author(s):

Harry I. A. Chen ◽

Edward K. W. Loo ◽

James B. Kuo ◽

Marek J. Syrzycki

Keyword(s):

Low Power ◽

High Speed ◽

High Level Synthesis ◽

Power Minimization ◽

Minimization Technique ◽

Static Power ◽

High Level

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Register allocation for high-level synthesis using dual supply voltages

Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09 ◽

10.1145/1629911.1630152 ◽

2009 ◽

Cited By ~ 7

Author(s):

Insup Shin ◽

Seungwhun Paik ◽

Youngsoo Shin

Keyword(s):

High Level Synthesis ◽

Supply Voltages ◽

High Level

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Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-74442-9_44 ◽

2007 ◽

pp. 453-462 ◽

Cited By ~ 3

Author(s):

Harry I. A. Chen ◽

Edward K. W. Loo ◽

James B. Kuo ◽

Marek J. Syrzycki

Keyword(s):

High Level Synthesis ◽

Power Minimization ◽

Static Power ◽

High Level

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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