Asynchronous Design Methodology for an Efficient Implementation of Low power ALU

2006 ◽  
Author(s):  
P. Manikandan ◽  
B.D. Liu ◽  
L. Y. Chiou ◽  
G. Sundar ◽  
C. R. Mandal
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Efficient Implementation ◽  
Asynchronous Design

Design Methodology for Voltage-Overscaled Ultra-Low-Power Systems

2012 ◽  
Vol 59 (12) ◽  
pp. 952-956 ◽  
Author(s):  
Dongsuk Jeon ◽  
Mingoo Seok ◽  
Zhengya Zhang ◽  
David Blaauw ◽  
Dennis Sylvester
Keyword(s):  
Power Systems ◽  
Low Power ◽  
Design Methodology ◽  
Ultra Low Power

Design methodology of ultra low-power MPEG4 codec core exploiting voltage scaling techniques

1998 ◽  
Author(s):  
Kimiyoshi Usami ◽  
Mutsunori Igarashi ◽  
Takashi Ishikawa ◽  
Masahiro Kanazawa ◽  
Masafumi Takahashi ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Voltage Scaling ◽  
Ultra Low Power

scholarly journals Low Power Design for ASIC Cores

VLSI Design ◽  
2001 ◽  
Vol 12 (3) ◽  
pp. 317-331
Author(s):  
Alvar Dean ◽  
David Garrett ◽  
Mircea R. Stan ◽  
Sebastian Ventrone
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Power Design ◽  
Clock Gating ◽  
Asic Design ◽  
Design Techniques

A semicustom ASIC design methodology is used to develop a low power DSP core for mobile (battery powered) applications. Different low power design techniques are used, including dual voltage, low power library elements, accurate power reporting, pseudomicrocode, transition-once logic, clock gating, and others.

scholarly journals A new interfacing circuit for low power asynchronous design in sensor systems

2014 ◽  
Vol 19 (1) ◽  
pp. 61-67 ◽  
Author(s):  
Jeong Tak Ryu ◽  
Won Kee Hong ◽  
Byung Ho Kang ◽  
Kyung Ki Kim
Keyword(s):  
Low Power ◽  
Sensor Systems ◽  
Asynchronous Design

scholarly journals Design of Completion Detectors in Asynchronous Communication System

2020 ◽  
Vol 9 (3) ◽  
pp. 3329-3334
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Communication System ◽  
Implementation Process ◽  
Asynchronous Communication ◽  
Digital Design ◽  
Low Power Consumption ◽  
Asynchronous Design ◽  
Global Clock ◽  
On Chip

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation.

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