Remote low-power digital design system

2015 ◽  
Author(s):  
Shatha AbuShanab ◽  
Marco Winzker ◽  
Rainer Bruck
Keyword(s):  
Low Power ◽  
Digital Design ◽  
Design System

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

scholarly journals Digital System Design for Traffic Light Controller System: A Systematic Approach

2021 ◽  
Vol 11 (11) ◽  
pp. 169-175
Author(s):  
To Nhi Ho. T ◽  
◽  
Giao N. Pham ◽  
Quang Hung Nguyen ◽  
Binh A.Nguyen ◽  
...  
Keyword(s):  
System Design ◽  
Design Education ◽  
Finite State Machine ◽  
State Machine ◽  
Digital System ◽  
Digital Design ◽  
Design System ◽  
Traffic Light ◽  
Finite State ◽  
Digital System Design

In this paper, we are going to present the finite state machine, how to implement it via hardware description language (HDL), and how to use it in a real application. At first, the specification and requirements of traffic light controller are stated. Then, the system architecture based on finite state machine (FSM) are conducted. Finally, the way of using HDL as well as the test-bench simulation are given in detail. Keywords : Digital system design, System on chip, Finite State Machine, Digital Design Education, Smart Classroom.

scholarly journals Design of Completion Detectors in Asynchronous Communication System

2020 ◽  
Vol 9 (3) ◽  
pp. 3329-3334
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Communication System ◽  
Implementation Process ◽  
Asynchronous Communication ◽  
Digital Design ◽  
Low Power Consumption ◽  
Asynchronous Design ◽  
Global Clock ◽  
On Chip

In digital design, there are two types of design, synchronous design and asynchronous design. In synchronous design, global clock is one of the main system that consume a lot of power. The power in synchronous design is consumed by clock even if there is no data processing take place. The asynchronous design that depends on data is clockless and as far as the power is concerned, asynchronous design does not consume much power compared with synchronous design and this really make asynchronus design the preffered choice for low power consumption. Besides having low power consumption, there are many advantages of aynchronous design compared with synchronous design. This paper proposed new dual rail completion detector (CD), 3-6 CD, 2-7 CD and 1-4 CD for on-chip communication that are used widely in an asynchronous communication system. The design of CD is based on the principle of sum adder. The circuit is designed by using Altera Quartus II CAD tools, synthesis and implementation process is executed to check the syntax error of the design. The design proved to be successful by using asynchronous on-chip communication in the simulation.

scholarly journals Recent Subthreshold Design Techniques

2012 ◽  
Vol 2012 ◽  
pp. 1-11 ◽  
Author(s):  
Mohsen Radfar ◽  
Kriyang Shah ◽  
Jugdutt Singh
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Large Scale ◽  
Vlsi Circuits ◽  
Digital Design ◽  
Future Directions ◽  
Significant Development ◽  
Rapid Pace ◽  
Catch Up ◽  
Subthreshold Design

Considering the variety of studies that have been reported in low-power designing era, the subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a significant development in recent years. Growing need for the lowest power consumption has been the primary motivation for increase in research in this area although other goals, such as lowest energy delay production, have also been achieved through sub-threshold design. There are, however, few extensive studies that provide a comprehensive design insight to catch up with the rapid pace and large-scale implementations of sub-threshold digital design methodology. This paper presents a complete review of recent studies in this field and explores all aspects of sub-threshold design methodology. Moreover, near-threshold design and low-power pipelining are also considered to provide a general review of sub-threshold applications. At the end, a discussion about future directions in ultralow-power design is also included.

Optimized Design of Low Power Complementary Metal Oxide Semiconductor Low Noise Amplifier for Zigbee Application

2021 ◽  
Vol 18 (4) ◽  
pp. 1327-1330
Author(s):  
S. Manjula ◽  
R. Karthikeyan ◽  
S. Karthick ◽  
N. Logesh ◽  
M. Logeshkumar
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Oxide Semiconductor ◽  
Design System ◽  
Cmos Process ◽  
Design Specifications ◽  
Noise Amplifier

An optimized high gain low power low noise amplifier (LNA) is presented using 90 nm CMOS process at 2.4 GHz frequency for Zigbee applications. For achieving desired design specifications, the LNA is optimized by particle swarm optimization (PSO). The PSO is successfully implemented for optimizing noise figure (NF) when satisfying all the design specifications such as gain, power dissipation, linearity and stability. PSO algorithm is developed in MATLAB to optimize the LNA parameters. The LNA with optimized parameters is simulated using Advanced Design System (ADS) Simulator. The LNA with optimized parameters produces 21.470 dB of voltage gain, 1.031 dB of noise figure at 1.02 mW power consumption with 1.2 V supply voltage. The comparison of designed LNA with and without PSO proves that the optimization improves the LNA results while satisfying all the design constraints.

Design of Digital Operational Units with Low Power Consumption

2021 ◽  
Vol 12 (2) ◽  
pp. 63-73
Author(s):  
N. A. Avdeev ◽  
◽  
P. N. Bibilo ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Digital Design ◽  
Low Power Consumption ◽  
Structural Description ◽  
Clock Gating ◽  
Vhdl Code

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

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