Design and implementation of matrix algorithms of systolic array processor

Mapping Intimacies ◽

10.1109/ace.1990.762687 ◽

2005 ◽

Author(s):

K. Chiranjeevi ◽

C.V. Kameshwara Rao

Keyword(s):

Systolic Array ◽

Array Processor ◽

Design And Implementation ◽

Matrix Algorithms

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Multiple Signal Classification (MUSIC) Algorithm Hosted On The High Speed Systolic Array Processor (HISSAP)

10.1117/12.948565 ◽

1989 ◽

Author(s):

Joseph P. Loughlin

Keyword(s):

Systolic Array ◽

High Speed ◽

Signal Classification ◽

Array Processor ◽

Music Algorithm ◽

Multiple Signal Classification ◽

Multiple Signal

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A Two-dimensional Systolic Array Processor for Image Processing

The Fifth International Conference on VLSI Design ◽

10.1109/icvd.1992.658050 ◽

2005 ◽

Cited By ~ 5

Author(s):

N. Ranganathan ◽

M. Patell ◽

P.A. McCabe

Keyword(s):

Image Processing ◽

Systolic Array ◽

Two Dimensional ◽

Array Processor

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Locally Parallel Image-Processing in Large-Scale Systolic Array Processor

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss1987.113.11_933 ◽

1993 ◽

Vol 113 (11) ◽

pp. 933-938

Author(s):

Yoshihiro Okada ◽

Toshiyuki Sakai

Keyword(s):

Image Processing ◽

Systolic Array ◽

Large Scale ◽

Array Processor ◽

Parallel Image Processing ◽

Parallel Image

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A Novel Technique for Mean Filter Design and Implementation via. Systolic Array

Journal of Engineering and Applied Sciences ◽

10.36478/jeasci.2019.9529.9537 ◽

2019 ◽

Vol 14 (24) ◽

pp. 9529-9537

Author(s):

Asmaa Hameed Rasheed

Keyword(s):

Systolic Array ◽

Filter Design ◽

Design And Implementation ◽

Novel Technique ◽

Mean Filter

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Multipath suppression performance of an adaptive array antenna with a systolic array processor

Electronics and Communications in Japan (Part I Communications) ◽

10.1002/ecja.4410761109 ◽

1993 ◽

Vol 76 (11) ◽

pp. 95-104

Author(s):

Manabu Ohmiya ◽

Tatsuya Kawabata ◽

Yasutaka Ogawa ◽

Kiyohiko Itoh

Keyword(s):

Systolic Array ◽

Array Antenna ◽

Adaptive Array ◽

Array Processor

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Optical Systolic Array Processor Designs For The Linear Estimation Of Data Sequences

10.1117/12.944022 ◽

1984 ◽

Author(s):

Steven C. Gustafson

Keyword(s):

Systolic Array ◽

Array Processor ◽

Linear Estimation ◽

Processor Designs

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Design and implementation of a parallel image processor chip for a SIMD array processor

Proceedings The International Conference on Application Specific Array Processors ◽

10.1109/asap.1995.522906 ◽

2002 ◽

Cited By ~ 5

Author(s):

M.H. Sunwoo ◽

Soohwan Ong ◽

Byungdug Ahn ◽

Kyungwoo Lee

Keyword(s):

Array Processor ◽

Image Processor ◽

Design And Implementation ◽

Parallel Image

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FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications ◽

10.1109/tcsi.2004.838266 ◽

2005 ◽

Vol 52 (2) ◽

pp. 350-365 ◽

Cited By ~ 19

Author(s):

Man Guo ◽

M.O. Ahmad ◽

M.N.S. Swamy ◽

Chunyan Wang

Keyword(s):

Low Power ◽

Systolic Array ◽

Viterbi Decoder ◽

Fpga Design ◽

Design And Implementation

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Parallel factorization of banded linear matrices using a systolic array processor

Advances in Computational Mathematics ◽

10.1007/bf02124732 ◽

1996 ◽

Vol 5 (1) ◽

pp. 1-14

Author(s):

I. J. Anderson ◽

S. K. Harbour

Keyword(s):

Systolic Array ◽

Array Processor ◽

Parallel Factorization

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A Speed-Optimized Systolic Array Processor Architecture for Spatio-Temporal 2-D IIR Broadband Beam Filters

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2008.918214 ◽

2008 ◽

Vol 55 (7) ◽

pp. 1953-1966 ◽

Cited By ~ 43

Author(s):

H.L.P. Arjuna Madanayake ◽

L.T. Bruton

Keyword(s):

Systolic Array ◽

Array Processor ◽

Processor Architecture ◽

Spatio Temporal

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