scholarly journals Machine-Learning-Based Read Reference Voltage Estimation for NAND Flash Memory Systems Without Knowledge of Retention Time

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 176416-176429
Author(s):  
Hyemin Choe ◽  
Jeongju Jee ◽  
Seung-Chan Lim ◽  
Sung Min Joe ◽  
Il Han Park ◽  
...  
Keyword(s):  
Machine Learning ◽  
Retention Time ◽  
Flash Memory ◽  
Memory Systems ◽  
Reference Voltage ◽  
Nand Flash ◽  
Nand Flash Memory

scholarly journals A Block Classification Method with Monitor and Restriction in NAND Flash memory

2021 ◽  
Vol 12 (5) ◽  
pp. 209-215
Author(s):  
Myungsub Lee
Keyword(s):  
Performance Evaluation ◽  
Standard Deviation ◽  
Flash Memory ◽  
Garbage Collection ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Wear Leveling ◽  
Block Classification ◽  
Update Frequency

In this paper, we propose a block classification with monitor and restriction (BCMR) method to isolate and reduce the interference of blocks in garbage collection and wear leveling. The proposed method monitors the endurance variation of blocks during garbage collection and detects hot blocks by making a restriction condition based on this information. This method induces block classification by its update frequency for garbage collection and wear leveling, resulting in a prolonged lifespan for NAND flash memory systems. The performance evaluation results show that the BCMR method prolonged the life of NAND flash memory systems by 3.95% and reduced the standard deviation per block by 7.4%, on average.

scholarly journals Machine Learning-Based Optimization Technique for High-Capacity V-NAND Flash Memory

2021 ◽  
Author(s):  
Jisuk Kim ◽  
Earl Kim ◽  
Daehyeon Lee ◽  
Taeheon Lee ◽  
Daesik Ham ◽  
...  
Keyword(s):  
Machine Learning ◽  
Genetic Algorithm ◽  
Flash Memory ◽  
State Of The Art ◽  
Optimization Technique ◽  
High Capacity ◽  
Turnaround Time ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
The Individual

Abstract In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) should be tuned in order to optimize performance and validity. In this paper, we propose a machine learning-based optimization technique that can automatically tune the individual eFuse value based on a deep learning and genetic algorithm. Using state-of-the-art triple-level cell (TLC) V-NAND flash wafers, we trained our model and validated its effectiveness. The experimental results show that our technique can automatically optimize NAND flash memory, thus reducing total turnaround time (TAT) by 70 % compared with the manual-based process.

Using adaptive read voltage thresholds to enhance the reliability of MLC NAND flash memory systems

2014 ◽  
Author(s):  
Nikolaos Papandreou ◽  
Thomas Parnell ◽  
Haralampos Pozidis ◽  
Thomas Mittelholzer ◽  
Evangelos Eleftheriou ◽  
...  
Keyword(s):  
Flash Memory ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory

A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory

2021 ◽  
Vol 26 (5) ◽  
pp. 1-25
Author(s):  
Chin-Hsien Wu ◽  
Hao-Wei Zhang ◽  
Chia-Wei Liu ◽  
Ta-Ching Yu ◽  
Chi-Yen Yang
Keyword(s):  
Machine Learning ◽  
Flash Memory ◽  
Huffman Coding ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Compression Performance ◽  
Learning From Data ◽  
Physical Problems ◽  
Coding Method ◽  
Multi Level

With the progress of the manufacturing process, NAND flash memory has evolved from the single-level cell and multi-level cell into the triple-level cell (TLC). NAND flash memory has physical problems such as the characteristic of erase-before-write and the limitation of program/erase cycles. Moreover, TLC NAND flash memory has low reliability and short lifetime. Thus, we propose a dynamic Huffman coding method that can apply to the write operations of NAND flash memory. The proposed method exploits observations from a Huffman tree and machine learning from data patterns to dynamically select a suitable Huffman coding. According to the experimental results, the proposed method can improve the reliability of TLC NAND flash memory and also consider the compression performance for those applications that require the Huffman coding.

scholarly journals Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1152
Author(s):  
Fei Chen ◽  
Bo Chen ◽  
Hongzhe Lin ◽  
Yachen Kong ◽  
Xin Liu ◽  
...  
Keyword(s):  
Flash Memory ◽  
Temperature Effects ◽  
Memory Systems ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Flash Memories ◽  
Charge Trap ◽  
Fundamental Factor ◽  
Temperature Impacts ◽  
Raw Bit Error Rate

Temperature effects should be well considered when designing flash-based memory systems, because they are a fundamental factor that affect both the performance and the reliability of NAND flash memories. In this work, aiming to comprehensively understanding the temperature effects on 3D NAND flash memory, triple-level-cell (TLC) mode charge-trap (CT) 3D NAND flash memory chips were characterized systematically in a wide temperature range (−30~70 °C), by focusing on the raw bit error rate (RBER) degradation during program/erase (P/E) cycling (endurance) and frequent reading (read disturb). It was observed that (1) the program time showed strong dependences on the temperature and P/E cycles, which could be well fitted by the proposed temperature-dependent cycling program time (TCPT) model; (2) RBER could be suppressed at higher temperatures, while its degradation weakly depended on the temperature, indicating that high-temperature operations would not accelerate the memory cells’ degradation; (3) read disturbs were much more serious at low temperatures, while it helped to recover a part of RBER at high temperatures.

scholarly journals A Relative Reference Responsive LRU based Page Replacement Algorithm for NAND Flash Memory

Webology ◽  
2021 ◽  
Vol 18 (1) ◽  
pp. 62-76
Author(s):  
Hitha Paulson ◽  
Dr.R. Rajesh
Keyword(s):  
Flash Memory ◽  
Memory Systems ◽  
Management Technique ◽  
Hard Disks ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Replacement Algorithm ◽  
Replacement Procedure ◽  
Replacement Algorithms ◽  
Fast Access

The acceptance of NAND flash memories in the electronic world, due to its non-volatility, high density, low power consumption, small size and fast access speed is hopeful. Due to the limitations in life span and wear levelling, this memory needs special attention in its management techniques compared to the conventional techniques used in hard disks. In this paper, an efficient page replacement algorithm is proposed for NAND flash based memory systems. The proposed algorithm focuses on decision making policies based on the relative reference ratio of pages in memory. The size adjustable eviction window and the relative reference based shadow list management technique proposed by the algorithm contribute much to the efficiency in page replacement procedure. The simulation tool based experiments conducted shows that the proposed algorithm performs superior to the well-known flash based page replacement algorithms with regard to page hit ratio and memory read/write operations.

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