scholarly journals DC-Patch: A Microarchitectural Fault Patching Technique for GPU Register Files

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 173276-173288
Author(s):  
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Dario Suarez-Gracia ◽  
Ruben Gran-Tejero
Keyword(s):  
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Code scheduling for VLIW/superscalar processors with limited register files

1992 ◽  
Vol 23 (1-2) ◽  
pp. 197-201
Author(s):  
Tokuzo Kiyohara ◽  
John C. Gyllenhaal
Keyword(s):  
Superscalar Processors ◽  
Register Files ◽  
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Area and Timing Estimation in Register Files Using Neural Networks

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pp. 269-277
Author(s):  
Assim Sagahyroon ◽  
Jamal Abdalla
Keyword(s):  
Neural Networks ◽  
Timing Estimation ◽  
Register Files

scholarly journals Low power register files by eliminating redundant read

2014 ◽  
Vol 11 (18) ◽  
pp. 20140774-20140774
Author(s):  
Leiou Wang ◽  
Donghui Wang ◽  
Huan Ying ◽  
Chengpeng Hao
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Low Power ◽  
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Early Register Deallocation Mechanisms Using Checkpointed Register Files

2006 ◽  
Vol 55 (9) ◽  
pp. 1153-1166 ◽  
Author(s):  
O. Ergin ◽  
D. Balkan ◽  
D. Ponomarev ◽  
K. Ghose
Keyword(s):  
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