scholarly journals LW-DEM: Designing a Low Power Digital-to-Analog Converter Using Lightweight Dynamic Element Matching Technique

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 112617-112628 ◽  
Author(s):  
Dong-Hyun Yoon ◽  
Dong-Kyu Jung ◽  
Bo-Yun Jung ◽  
Ji-Min Choi ◽  
Yong-Jun Jo ◽  
...  
Keyword(s):  
Low Power ◽  
Dynamic Element Matching ◽  
Digital To Analog Converter ◽  
Matching Technique ◽  
Analog Converter ◽  
Digital To Analog ◽  
Dynamic Element

A low-power MPEG audio layer III decoder IC with an integrated digital-to-analog converter

2000 ◽  
Vol 46 (3) ◽  
pp. 896-902 ◽  
Author(s):  
J. Takala ◽  
J. Rostrom ◽  
T. Vaaraniemi ◽  
H. Herranen ◽  
P. Ojala
Keyword(s):  
Low Power ◽  
Digital To Analog Converter ◽  
Analog Converter ◽  
Digital To Analog

Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt
Keyword(s):  
Low Power ◽  
High Speed ◽  
Wireless Transceivers ◽  
Digital To Analog Converter ◽  
Bicmos Technology ◽  
Analog Converter ◽  
Sige Bicmos ◽  
Digital To Analog ◽  
On Chip ◽  
Binary Weighted

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

Sign in / Sign up

Export Citation Format

Share Document