P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings

IEEE Access ◽

10.1109/access.2018.2890112 ◽

2019 ◽

Vol 7 ◽

pp. 6816-6830

Author(s):

Louis Y.-Z. Lin ◽

Charles Chia-Hao Hsu ◽

Charles H.-P. Wen

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Parallel Test

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Parallel test pattern generation using circuit partitioning in a shared-memory multiprocessor

Lecture Notes in Computer Science - Applied Parallel Computing Large Scale Scientific and Industrial Problems ◽

10.1007/bfb0095334 ◽

1998 ◽

pp. 167-171 ◽

Cited By ~ 1

Author(s):

Consolación Gil ◽

Julio Ortega ◽

Jose Luis Bernier ◽

Maria Dolores Gil

Keyword(s):

Shared Memory ◽

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Circuit Partitioning ◽

Parallel Test ◽

Shared Memory Multiprocessor

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Bit parallel test pattern generation for path delay faults

Proceedings the European Design and Test Conference. ED&TC 1995 ◽

10.1109/edtc.1995.470351 ◽

2002 ◽

Cited By ~ 9

Author(s):

M. Henftling ◽

H. Wittman

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Delay Faults ◽

Path Delay ◽

Path Delay Faults ◽

Parallel Test

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Parallel test pattern generation using Boolean satisfiability

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185095 ◽

1991 ◽

Cited By ~ 3

Author(s):

V. Sivaramakrishnan ◽

S.C. Seth ◽

P. Agrawal

Keyword(s):

Test Pattern ◽

Boolean Satisfiability ◽

Pattern Generation ◽

Test Pattern Generation ◽

Parallel Test

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A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2011.2157693 ◽

2011 ◽

Vol 30 (11) ◽

pp. 1767-1772 ◽

Cited By ~ 10

Author(s):

Kuan-Yu Liao ◽

Chia-Yuan Chang ◽

J. C-M Li

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Generation Algorithm ◽

Parallel Test

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Test pattern generation for logic crosstalk faults in VLSI circuits

IEE Proceedings G Circuits Devices and Systems ◽

10.1049/ip-g-2.1991.0034 ◽

1991 ◽

Vol 138 (2) ◽

pp. 179 ◽

Cited By ~ 3

Author(s):

A. Rubio ◽

J.A. Sainz ◽

K. Kinoshita

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Vlsi Circuits ◽

Test Pattern Generation

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Test the S27 Benchmark Circuit by Using Built In Self Test and Test Pattern Generation

International Journal of Advanced Research in Electrical Electronics and Instrumentation Engineering ◽

10.15662/ijareeie.2014.0308083 ◽

2014 ◽

Vol 03 (08) ◽

pp. 11487-11495

Author(s):

S. Nagaraju ◽

Ch.N.L. Sujatha ◽

J.S.S. Ramaraju

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Benchmark Circuit ◽

Self Test ◽

Built In Self Test

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Machine Intelligence for Efficient Test Pattern Generation

2020 IEEE International Test Conference (ITC) ◽

10.1109/itc44778.2020.9325250 ◽

2020 ◽

Author(s):

Soham Roy ◽

Spencer K. Millican ◽

Vishwani D. Agrawal

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Machine Intelligence ◽

Test Pattern Generation ◽

Efficient Test

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An automatic test pattern generation framework for combinational threshold logic networks

IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. ◽

10.1109/iccd.2004.1347974 ◽

2004 ◽

Cited By ~ 6

Author(s):

P. Gupta ◽

Rui Zhang ◽

N.K. Jha

Keyword(s):

Test Pattern ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automatic Test Pattern Generation ◽

Threshold Logic ◽

Automatic Test

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Analysis of optimization algorithms in automated test pattern generation for sequential circuits

2017 IEEE International Conference on Systems, Man, and Cybernetics (SMC) ◽

10.1109/smc.2017.8122883 ◽

2017 ◽

Cited By ~ 1

Author(s):

Majed M. Alateeq ◽

Witold Pedrycz

Keyword(s):

Test Pattern ◽

Optimization Algorithms ◽

Sequential Circuits ◽

Pattern Generation ◽

Test Pattern Generation ◽

Automated Test

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Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams

International Journal of High Performance Systems Architecture ◽

10.1504/ijhpsa.2016.076204 ◽

2016 ◽

Vol 6 (1) ◽

pp. 51 ◽

Cited By ~ 3

Author(s):

J.P. Anita ◽

P. Sudheesh

Keyword(s):

Test Pattern ◽

Power Reduction ◽

Pattern Generation ◽

Test Pattern Generation ◽

Decision Diagrams ◽

Test Power ◽

Multiple Faults ◽

Test Power Reduction

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