A parallel embedded-processor architecture for ATM reassembly

1999 ◽  
Vol 7 (1) ◽  
pp. 23-37 ◽  
Author(s):  
R.F. Hobson ◽  
P.S. Wong
Keyword(s):  
Processor Architecture ◽  
Embedded Processor

scholarly journals Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

2020 ◽  
Author(s):  
Sven Gesper ◽  
Moritz Weißbrich ◽  
Tobias Stuckenberg ◽  
Pekka Jääskeläinen ◽  
Holger Blume ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Cmos Technology ◽  
Control Flow ◽  
Processor Architecture ◽  
Embedded Processor ◽  
Silicon Area ◽  
Trade Offs ◽  
Advanced Control ◽  
Flow Mechanisms ◽  
Technology Nodes

AbstractMicrocontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 $$\upmu $$ μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5$$\times $$ × higher performance and 2.4$$\times $$ × higher computational energy efficiency at a 1.6$$\times $$ × larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

Embedded-processor architecture for parallel DSP algorithms

1996 ◽  
Author(s):  
Rick F. Hobson ◽  
Peter S. Wong ◽  
S. A. Evenson
Keyword(s):  
Processor Architecture ◽  
Embedded Processor
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