Next Generation Embedded Processor Architecture for Personal Information Devices

2006 ◽  
pp. 459-468
Author(s):  
In-Pyo Hong ◽  
Yong-Joo Lee ◽  
Yong-Surk Lee
Keyword(s):  
Personal Information ◽  
Processor Architecture ◽  
Next Generation ◽  
Embedded Processor

scholarly journals Assessing the Treatment of Patron Privacy in Library 2.0 Literature

2013 ◽  
Vol 32 (2) ◽  
pp. 29 ◽  
Author(s):  
Michael Zimmer
Keyword(s):  
Web 2.0 ◽  
Personal Information ◽  
Intellectual Freedom ◽  
Next Generation ◽  
Web 2.0 Technologies ◽  
Professional Discourse ◽  
Related Information ◽  
Information Professionals

<p>As libraries begin to embrace Web 2.0 technologies to serve patrons – ushering in the era of Library 2.0 – unique dilemmas arise regarding protection of patron privacy. The norms of Web 2.0 promote the open sharing of information – often personal information – and the design of many Library 2.0 services capitalize on access to patron information and might require additional tracking, collection and aggregation of patron activities. Thus, embracing Library 2.0 potentially threatens the traditional ethics of librarianship, where protecting patron privacy and intellectual freedom has been held paramount. As a step towards informing the decisions to implement Library 2.0 to adequately protect patron privacy, we must first understand how such concerns are being articulated within the professional discourse surrounding these next generation library tools and services. The study presented in this paper aims to determine whether and how issues of patron privacy are introduced, discussed, and settled – if at all – within trade publications utilized by librarians and related information professionals</p>

IoMT, Edge Computing, Blockchain, and Deep Learning for Next Generation Healthcare Systems (Preprint)

2021 ◽  
Author(s):  
Mohammad (Behdad) Jamshidi ◽  
Tarek Frikha ◽  
Asal Sabet ◽  
Omar Cheikhrouhou ◽  
Habib Hamam
Keyword(s):  
Intelligent Systems ◽  
Personal Information ◽  
Healthcare Systems ◽  
Cyber Attacks ◽  
Edge Computing ◽  
Medical Documentation ◽  
Next Generation ◽  
Healthcare Data ◽  
Smart Healthcare ◽  
Flexible Infrastructure

UNSTRUCTURED Processing medical data, diagnosing diseases, determining the best possible medical centers or physicians, and recommending the more effective remedies or drugs in the earliest time are the most important challenges to deploy intelligent systems for healthcare purposes. Hence, utilization of the Internet of Medical Things (IoMT) with Edge Computing (EC) technology will result in a strong network to aggregate the healthcare data more reliably and solve the aforementioned challenges. However, the administration of the millions of individuals with a wide variety of physical or mental disorders is another challenge associated with the use of such Artificial Intelligence-based platforms, especially when it comes to a large number of insurance conditions and companies. Furthermore, although the EC-based platforms can increase the security of the data, there are still vulnerable to face some cyber-attacks. Thus, the privacy of sensitive personal information of patients should be considered. Blockchain is a suitable option to overcome the problems associated with medical documentation and administration of patient’s affairs using smart contracts. An EC-based platform based on blockchain to improve the weaknesses of conventional smart healthcare systems is rendered in this research. The proposed platform takes the advantage of both EC and blockchain in the terms of speed, security, accuracy, and bandwidth. It should be noted that this method could be utilized as a flexible infrastructure for the next generation healthcare systems using any kind of crypto network like Bitcoin, Ethereum, Cardano, etc.

A Next-Generation Cryogenic Processor Architecture

IEEE Micro ◽  
2021 ◽  
pp. 1-1
Author(s):  
Ilkwon Byun ◽  
Dongmoon Min ◽  
Gyu-hyeon Lee ◽  
Seongmin Na ◽  
Jangwoo Kim
Keyword(s):  
Processor Architecture ◽  
Next Generation

scholarly journals Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments

2020 ◽  
Author(s):  
Sven Gesper ◽  
Moritz Weißbrich ◽  
Tobias Stuckenberg ◽  
Pekka Jääskeläinen ◽  
Holger Blume ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Cmos Technology ◽  
Control Flow ◽  
Processor Architecture ◽  
Embedded Processor ◽  
Silicon Area ◽  
Trade Offs ◽  
Advanced Control ◽  
Flow Mechanisms ◽  
Technology Nodes

AbstractMicrocontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS- or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 $$\upmu $$ μ m SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transport-triggered architecture configuration has an 8.5$$\times $$ × higher performance and 2.4$$\times $$ × higher computational energy efficiency at a 1.6$$\times $$ × larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

Sign in / Sign up

Export Citation Format

Share Document