An analytical model for current, delay, and power analysis of submicron CMOS logic circuits

2000 ◽  
Vol 47 (10) ◽  
pp. 999-1007 ◽  
Author(s):  
A.A. Hamoui ◽  
N.C. Rumin
Keyword(s):  
Analytical Model ◽  
Power Analysis ◽  
Logic Circuits ◽  
Submicron Cmos

scholarly journals Performance and power analysis for high performance computation benchmarks

2013 ◽  
Vol 3 (1) ◽  
pp. 1-16
Author(s):  
Joseph Issa
Keyword(s):  
Power Consumption ◽  
Analytical Model ◽  
Power Analysis ◽  
High Performance ◽  
Measured Data ◽  
Performance Model ◽  
Performance Estimation ◽  
And Behavior ◽  
Performance Computing ◽  
High Performance Computation

AbstractPerformance and power consumption analysis and characterization for computational benchmarks is important for processor designers and benchmark developers. In this paper, we characterize and analyze different High Performance Computing workloads. We analyze benchmarks characteristics and behavior on various processors and propose a performance estimation analytical model to predict performance for different processor microarchitecture parameters. Performance model is verified to predict performance within <5% error margin between estimated and measured data for different processors. We also propose a power estimation analytical model to estimate power consumption with low error deviation.

scholarly journals Static Power Research on Nano Cryptographic Circuits

2019 ◽  
Vol 8 (2S3) ◽  
pp. 1241-1245
Keyword(s):  
Integrated Circuits ◽  
Analytical Model ◽  
Integrated Circuit ◽  
Data Security ◽  
Power Loss ◽  
Power Analysis ◽  
Leakage Power ◽  
Secret Key ◽  
Power Models ◽  
Static Power

In this present static power analysis of Nano circuit is presented. The attack is bused to obtain the secret key of a cryptographic core by measuring static power loss. These attack take leakage current from the integrated circuit depends upon input to extract secrete key called as Leakage Power Analysis (LPA) Since the leakage power expands a lot quicker than the dynamic power at each new innovation age, LPA assaults are a genuine risk to the data security of cryptographic circuits in sub-100-nm advancements. In this paper a leakage power attack is well demonstrated and simulated on different integrated circuits and an analytical model of LPA attack is presented to understand the effectiveness of this technique as a threat to cryptographic integrated circuits . The effect of innovation scaling is expressly tended to by methods for a straightforward analytical model and Monte Carlo simulation. Simulation on a 45nm, 65-and 90-nm technology and trial-experimental results are introduced to legitimize the suppositions and approve the leakage power models

scholarly journals Asynchronous AES Crypto-Processor Including Secured and Optimized Blocks

2004 ◽  
Vol 1 (1) ◽  
pp. 5-13
Author(s):  
Fraidy Bouesse ◽  
M. Renaudin ◽  
Fabien Germain
Keyword(s):  
Power Analysis ◽  
Design Methodology ◽  
Asynchronous Circuits ◽  
Logic Circuits ◽  
Data Path ◽  
Constant Number ◽  
Hardware Cost ◽  
Fundamental Properties ◽  
Trade Offs ◽  
Simulation Results

This paper presents the first study of an asynchronous AES architecture compliant with the NIST standard. It exploits the fundamental properties of quasi delay insensitive asynchronous circuits. First, 1 to N encoding is extensively used in order to minimize hardware cost, thus optimizing area and speed. Most importantly, it is shown how the quasi delay insensitive logic style gives the opportunity to design balanced architectures, particularly well suited to improve differential power analysis resistance. Indeed, the proposed design methodology enables the generation of logic circuits which always involve a constant number of logical transitions, independently of data values processed by the circuit. Based on a 32-bit data-path, a balanced and optimized QDI asynchronous architecture of the AES is described. In addition, several architecture trade-offs are considered, and their area and speed estimated. Simulation results show that with the proposed design approach, throughputs ranging from 36 Mbit/s to more than 569 Mbit/s can be achieved, well suited to target smart-card applications.

Analytical model for switching transitions of submicron CMOS logics

1997 ◽  
Vol 32 (6) ◽  
pp. 880-889 ◽  
Author(s):  
Heung-Joon Park ◽  
M. Soma
Keyword(s):  
Analytical Model ◽  
Submicron Cmos

Symmetric Adiabatic Logic Circuits against Differential Power Analysis

ETRI Journal ◽  
2010 ◽  
Vol 32 (1) ◽  
pp. 166-168 ◽  
Author(s):  
Byong-Deok Choi ◽  
Kyung Eun Kim ◽  
Ki-Seok Chung ◽  
Dong Kyue Kim
Keyword(s):  
Power Analysis ◽  
Logic Circuits ◽  
Differential Power Analysis ◽  
Adiabatic Logic
Sign in / Sign up

Export Citation Format

Share Document