scholarly journals Analytical Models for Delay and Power Analysis of Zero-VGSLoad Unipolar Thin-Film Transistor Logic Circuits

2014 ◽  
Vol 61 (11) ◽  
pp. 3838-3844 ◽  
Author(s):  
Qingyu Cui ◽  
Radu A. Sporea ◽  
Wenjiang Liu ◽  
Xiaojun Guo
Materials ◽  
2019 ◽  
Vol 12 (23) ◽  
pp. 3815 ◽  
Author(s):  
Joo ◽  
Shin ◽  
Jung ◽  
Cha ◽  
Nam ◽  
...  

Numerous studies have addressed the utilization of oxide thin-film transistor (TFT)-based complementary logic circuits that are based on two-dimensional (2D) planar structures. However, there are fundamental limits to the 2D planar structured complementary logic circuits, such as a large dimension and a large parasitic resistance. This work demonstrated a vertically stacked three-dimensional complementary inverter composed of a p-channel tin monoxide (SnO) TFT and an n-channel indium-gallium-zinc oxide (IGZO) TFT. A bottom-gate p-channel SnO TFT was formed on the top-gate n-channel IGZO TFT with a shared common gate electrode. The fabricated vertically stacked complementary inverter exhibited full swing characteristics with a voltage gain of ~33.6, a high noise margin of 3.13 V, and a low noise margin of 3.16 V at a supplied voltage of 10 V. The achieved voltage gain of the fabricated complementary inverter was higher than that of the vertically stacked complementary inverters composed of other oxide TFTs in previous works. In addition, we showed that the vertically stacked complementary inverter exhibited excellent visible-light photoresponse. This indicates that the oxide TFT-based vertically stacked complementary inverter can be used as a sensitive photo-sensor operating in the visible spectral range with the voltage read-out scheme.


2015 ◽  
Vol 1107 ◽  
pp. 514-519
Author(s):  
Umar Faruk Shuib ◽  
Khairul Anuar Mohamad ◽  
Afishah Alias ◽  
Tamer A. Tabet ◽  
Bablu K. Gosh ◽  
...  

As organic transistors are preparing to make improvements towards flexible and low cost electronics applications, the analytical models and simulation methods were demanded to predict the optimized performance and circuit design. In this paper, we investigated the analytical model of an organic transistor device and simulate the output and transfer characteristics of the device using MATLAB tools for different channel length (L) of the organic transistor. In the simulation, the Pool-Frenkel mobility model was used to represent the conductive channel of organic transistor. The different channel length has been simulated with the value of 50 μm, 10 μm and 5 μm. This research paper analyses the performance of organic thin film transistor (TFT) for top contact bottom gate device. From the simulation, drain current of organic transistor was increased as the channel length decreased. Other extraction value such sub-threshold and current on/off ratio is 0.41 V and 21.1 respectively. Thus, the simulation provides significant extraction of information about the behaviour of the organic thin film transistor.


2013 ◽  
Vol 60 (5) ◽  
pp. 1782-1785 ◽  
Author(s):  
Qingyu Cui ◽  
Mengwei Si ◽  
Radu A. Sporea ◽  
Xiaojun Guo

2011 ◽  
Vol 1359 ◽  
Author(s):  
M. Raja ◽  
D. Donaghy ◽  
R. Myers ◽  
W. Eccleston

ABSTRACTWe present analytical models for organic thin film transistors (OTFTs) and Schottky diodes based on polycrystalline semiconductors. The OTFT model is developed using a well-established approach previously developed for polysilicon, with slight modification for organics. The model predicts voltage and temperature dependencies on the various device and circuit parameters. A good agreement is obtained with experimental data of TIPS-based OTFTs. Essential parameters such as the characteristic temperature and Meyer-Neldel Energy extracted using the model with TIPS OTFTs data were in agreement with those obtained from Schottky diode measurements.


Author(s):  
Youssef Ahmed Mobarak ◽  
Moamen Atef

<span>The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La<sub>2</sub>O<sub>3</sub>K<sub>ox</sub>=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO<sub>2</sub>K<sub>sp</sub>=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.</span>


2008 ◽  
Vol 128 (2) ◽  
pp. 213-219
Author(s):  
Hiroyuki Iechi ◽  
Yasuyuki Watanabe ◽  
Hiroshi Yamauchi ◽  
Kazuhiro Kudo

2009 ◽  
Vol 92 (9) ◽  
pp. 36-42
Author(s):  
Hiroyuki Iechi ◽  
Yasuyuki Watanabe ◽  
Hiroshi Yamauchi ◽  
Kazuhiro Kudo

2019 ◽  
Vol 673 ◽  
pp. 14-18 ◽  
Author(s):  
Hyeong Jun Cho ◽  
Dong-Hoon Lee ◽  
Eung-Kyu Park ◽  
Min Su Kim ◽  
So Young Lee ◽  
...  

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