High-speed operation of a 64-bit circular shift register

1998 ◽  
Vol 8 (3) ◽  
pp. 120-124 ◽  
Author(s):  
A.M. Herr ◽  
C.A. Mancini ◽  
N. Vukovic ◽  
M.F. Bocko ◽  
M.J. Feldman
Keyword(s):  
High Speed ◽  
Shift Register ◽  
Circular Shift Register

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

scholarly journals High Throughput Error Control Using Parallel CRC

VLSI Design ◽  
1994 ◽  
Vol 2 (1) ◽  
pp. 33-50
Author(s):  
Andrzej Sobski ◽  
Alexander Albicki
Keyword(s):  
High Throughput ◽  
High Speed ◽  
Error Control ◽  
Cyclic Codes ◽  
Shift Register ◽  
Linear Feedback ◽  
Clock Period ◽  
Feedback Shift Register ◽  
Parallel Stream ◽  
Speed Computer

Redesigning the LFSR (Linear Feedback Shift Register) so that syndrome calculations can be performed in one sweep allows for fast error control in high speed computer networks. The resulting structure forms the basis of the PEDDC (Parallel Encoder, Decoder, Detector, Corrector) which replaces the conventional Serial Encoder, Decoder, Detector, Corrector for generation and utilization of cyclic codes. Since syndromes are calculated in as little as one clock period, information from which the syndrome is calculated can be processed in a parallel stream. In this paper a simple PEDDC is built, its operation is examined in detail, its performance is compared with a serial counterpart, possible variations on the PEDDC structure is given, and further speed enhancement techniques are considered.

A 1.2 GHz high-speed 256-bit shift register LSI

2003 ◽  
Author(s):  
H. Mori ◽  
A. Tsukuda ◽  
H. Nishimura ◽  
M. Takada ◽  
Y. Kawakami ◽  
...  
Keyword(s):  
High Speed ◽  
Shift Register

Realization of All-Optical Circular Shift Register Using Semiconductor Optical Amplifiers

2011 ◽  
Vol 50 (11R) ◽  
pp. 110209 ◽  
Author(s):  
Ji Sok Lee ◽  
Jae Moon Lim ◽  
Ju Han Lee ◽  
Hyuk Jae Lee ◽  
Taek Jin Lee ◽  
...  
Keyword(s):  
Optical Amplifiers ◽  
Semiconductor Optical Amplifiers ◽  
Shift Register ◽  
All Optical ◽  
Circular Shift Register

scholarly journals High-speed test of SFQ-shift register files using PTL wiring

2004 ◽  
Vol 412-414 ◽  
pp. 1586-1590 ◽  
Author(s):  
K. Fujiwara ◽  
Y. Yamashiro ◽  
N. Yoshikawa ◽  
Y. Hashimoto ◽  
S. Yorozu ◽  
...  
Keyword(s):  
High Speed ◽  
Shift Register ◽  
Speed Test ◽  
Register Files
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