Chip layout design of a Josephson LSI circuit for examining high-speed operability by using a standard cell automatic placement and routing technique
1994 ◽
Vol 4
(3)
◽
pp. 169-176
◽
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2014 ◽
Vol 608-609
◽
pp. 933-936
2008 ◽
Vol 5
(1-4)
◽
pp. 325-337
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