Algorithmic and architectural enhancements for real-time MPEG-1 decoding on a general purpose RISC workstation

1995 ◽  
Vol 5 (5) ◽  
pp. 380-386 ◽  
Author(s):  
V. Bhaskaran ◽  
K. Konstantinides ◽  
R.B. Lee ◽  
J.P. Beck
Keyword(s):  
Real Time ◽  
General Purpose

Design and implementation of a virtual ARINC 653 simulation platform

SIMULATION ◽  
2021 ◽  
pp. 003754972199601
Author(s):  
Jinchao Chen ◽  
Keke Chen ◽  
Chenglie Du ◽  
Yifan Liu
Keyword(s):  
Real Time ◽  
System Development ◽  
General Purpose ◽  
Simulation Platform ◽  
Communication Management ◽  
Management Communication ◽  
Real Time Simulation ◽  
Testing And Debugging ◽  
Time Simulation ◽  
Efficiency And Effectiveness

The ARINC 653 operation system is currently widely adopted in the avionics industry, and has become the mainstream architecture in avionics applications because of its strong agility and reliability. Although ARINC 653 can efficiently reduce the weight and energy consumption, it results in a serious development and verification problem for avionics systems. As ARINC 653 is non-open source software and lacks effective support for software testing and debugging, it is of great significance to build a real-time simulation platform for ARINC 653 on general-purpose operating systems, improving the efficiency and effectiveness of system development and implementation. In this paper, a virtual ARINC 653 platform is designed and realized by using real-time simulation technology. The proposed platform is composed of partition management, communication management, and health monitoring management, provides the same operation interfaces as the ARINC 653 system, and allows dynamic debugging of avionics applications without requiring the actual presence of real devices. Experimental results show that the platform not only simulates the functionalities of ARINC 653, but also meets the real-time requirements of avionics applications.

Real-time MLton: A Standard ML runtime for real-time functional programs

2021 ◽  
Vol 31 ◽  
Author(s):  
BHARGAV SHIVKUMAR ◽  
JEFFREY MURPHY ◽  
LUKASZ ZIAREK
Keyword(s):  
Programming Languages ◽  
Real Time ◽  
Concurrency Control ◽  
General Purpose ◽  
Functional Languages ◽  
Control Mechanisms ◽  
Real Time Systems ◽  
Functional Programming Languages ◽  
Standard Ml ◽  
Time Systems

Abstract There is a growing interest in leveraging functional programming languages in real-time and embedded contexts. Functional languages are appealing as many are strictly typed, amenable to formal methods, have limited mutation, and have simple but powerful concurrency control mechanisms. Although there have been many recent proposals for specialized domain-specific languages for embedded and real-time systems, there has been relatively little progress on adapting more general purpose functional languages for programming embedded and real-time systems. In this paper, we present our current work on leveraging Standard ML (SML) in the embedded and real-time domains. Specifically, we detail our experiences in modifying MLton, a whole-program optimizing compiler for SML, for use in such contexts. We focus primarily on the language runtime, reworking the threading subsystem, object model, and garbage collector. We provide preliminary results over a radar-based aircraft collision detector ported to SML.

scholarly journals SoC-FPGA systems for the acquisition and processing of electroencephalographic signals

2021 ◽  
Vol 10 (3) ◽  
pp. 237
Author(s):  
Matias Javier Oliva ◽  
Pablo Andrés García ◽  
Enrique Mario Spinelli ◽  
Alejandro Luis Veiga
Keyword(s):  
Embedded System ◽  
Real Time ◽  
General Purpose ◽  
System Response ◽  
Single Chip ◽  
Real Time Processing ◽  
General Purpose Processor ◽  
Time Operation ◽  
Electroencephalographic Signals ◽  
High Level

<span lang="EN-US">Real-time acquisition and processing of electroencephalographic signals have promising applications in the implementation of brain-computer interfaces. These devices allow the user to control a device without performing motor actions, and are usually made up of a biopotential acquisition stage and a personal computer (PC). This structure is very flexible and appropriate for research, but for final users it is necessary to migrate to an embedded system, eliminating the PC from the scheme. The strict real-time processing requirements of such systems justify the choice of a system on a chip field-programmable gate arrays (SoC-FPGA) for its implementation. This article proposes a platform for the acquisition and processing of electroencephalographic signals using this type of device, which combines the parallelism and speed capabilities of an FPGA with the simplicity of a general-purpose processor on a single chip. In this scheme, the FPGA is in charge of the real-time operation, acquiring and processing the signals, while the processor solves the high-level tasks, with the interconnection between processing elements solved by buses integrated into the chip. The proposed scheme was used to implement a brain-computer interface based on steady-state visual evoked potentials, which was used to command a speller. The first tests of the system show that a selection time of 5 seconds per command can be achieved. The time delay between the user’s selection and the system response has been estimated at 343 µs.</span>

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