Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system

1998 ◽  
Vol 9 (8) ◽  
pp. 705-720 ◽  
Author(s):  
Keqin Li ◽  
Yi Pan ◽  
Si Qing Zheng
Keyword(s):  
Linear Array ◽  
Matrix Multiplication ◽  
Bus System

Modular Matrix Multiplication on a Linear Array.

1983 ◽  
Author(s):  
I. V. Ramakrishnan ◽  
P. J. Varman
Keyword(s):  
Linear Array ◽  
Matrix Multiplication

A PARALLEL ALGORITHM TO GENERATE N-ARY REFLECTED GRAY CODES IN A LINEAR ARRAY WITH RECONFIGURABLE BUS SYSTEM

1993 ◽  
Vol 03 (02) ◽  
pp. 157-164 ◽  
Author(s):  
P. THANGAVEL ◽  
V.P. MUTHUSWAMY
Keyword(s):  
Parallel Algorithm ◽  
Linear Array ◽  
Constant Time ◽  
Processor Array ◽  
Gray Codes ◽  
System A ◽  
Processor Arrays ◽  
Bus System

A simple parallel algorithm for generating N-ary reflected Gray codes is presented. The algorithm is derived from the pattern of N-ary reflected Gray codes. The algorithm runs on a linear processor array with a reconfigurable bus system. A reconfigurable bus system is a bus system whose configuration can be dynamically changed. Recently processor arrays with reconfigurable bus systems were used to solve many problems in constant time. There already exists experimental reconfigurable chips.

Implementation of a linear array element for matrix multiplication

Euro ASIC '91 ◽  
1991 ◽  
Author(s):  
M.A. Morante ◽  
L. Saiz de Quevedo ◽  
P. Tabuenca ◽  
J.I. Martinez ◽  
E. Villar
Keyword(s):  
Linear Array ◽  
Matrix Multiplication ◽  
Array Element
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