Improved method for the oxide thickness extraction in MOS structures with ultrathin gate dielectrics

2000 ◽  
Vol 13 (2) ◽  
pp. 152-158 ◽  
Author(s):  
G. Ghibaudo ◽  
S. Bruyere ◽  
T. Devoivre ◽  
B. DeSalvo ◽  
E. Vincent
2009 ◽  
Vol 95 (1) ◽  
pp. 012103 ◽  
Author(s):  
Chuan-Hsi Liu ◽  
Hung-Wen Chen ◽  
Shung-Yuan Chen ◽  
Heng-Sheng Huang ◽  
Li-Wei Cheng

2000 ◽  
Vol 639 ◽  
Author(s):  
D. Mistele ◽  
T. Rotter ◽  
R. Ferretti ◽  
F. Fedler ◽  
H. Klausing ◽  
...  

ABSTRACTPhotoanodically grown Ga2O3 layers were characterized with respect to their suitability as gate dielectrics for GaN based MOSFET Device applications. The Ga2O3 layers were produced in a photoelectrochemical cell using aqueous solutions of KOH. IV characterization of MOS structures show insulating behavior of the oxide layers and CV measurements indicate a small density of states at the oxide/GaN interface. Integrating the wet chemical oxide growth in a MOSFET device fabricating process includes tungsten as gate metal together with H2O2 as etching solution for the gate metal. Source/drain areas were made free of oxide by the alkaline developer of a conventional lithographic step and metallization was done by using the liftoff technique. MOS structures show no inversion mode but strong depletion in reverse biasing mode.


2013 ◽  
Vol 699 ◽  
pp. 422-425 ◽  
Author(s):  
K.C. Lin ◽  
C.H. Chou ◽  
J.Y. Chen ◽  
C.J. Li ◽  
J.Y. Huang ◽  
...  

In this research, the Y2O3 layer is doped with the zirconium through co-sputtering and rapid thermal annealing (RTA) at 550°C, 700°C, and 850°C. Then the Al electrode is deposited to generate two kinds of structures, Al/ZrN/ Y2O3/ Y2O3+Zr/p-Si and Al/ZrN/ Y2O3+Zr/ Y2O3/p-Si. According to the XRD results, when Zr was doped on the upper layer, the crystallization phenomenon was more significant than Zr was at the bottom layer, meaning that Zr may influence the diffusion of the oxygen. The AFM also shows that the surface roughness of Zr has worse performance. For the electrical property, the influence to overall leakage current is increased because the equivalent oxide thickness (EOT) is thinner.


1999 ◽  
Vol 595 ◽  
Author(s):  
W.P. Li ◽  
R. Zhang ◽  
J. Yin ◽  
X.H. Liu ◽  
Y.G. Zhou ◽  
...  

AbstractGaN-based metal-ferroelectric-semiconductor (MFS) structure has been fabricated by using ferroelectric Pb(Zr0.53Ti0.47)O3 (PZT) instead of conventional oxides as gate insulators. The GaN and PZT films in the MFS structures have been characterized by various methods such as photoluminescence (PL), wide-angle X-ray diffraction (XRD) and high-resolution X-ray diffraction (HRXRD). The Electric properties of GaN MFS structure with different oxide thickness have been characterized by high-frequency C-V measurement. When the PZT films are as thick as 1 µm, the GaN active layers can approach inversion under the bias of 15V, which can not be observed in the traditional GaN MOS structures. When the PZT films are about 100 nm, the MFS structures can approach inversion just under 5V. All the marked improvements of C-V behaviors in GaN MFS structures are mainly attributed to the high dielectric constant and large polarization of the ferroelectric gate oxide.


2006 ◽  
Vol 527-529 ◽  
pp. 987-990 ◽  
Author(s):  
Tsunenobu Kimoto ◽  
H. Kawano ◽  
Masato Noborio ◽  
Jun Suda ◽  
Hiroyuki Matsunami

Oxide deposition followed by high-temperature annealing in N2O has been investigated to improve the quality of 4H-SiC MOS structures. Annealing of deposited oxides in N2O at 1300oC significantly enhances the breakdown strength and decreases the interface state density to 3x1011 cm-2eV-1 at EC – 0.2 eV. As a result, high channel mobility of 34 cm2/Vs and 52 cm2/Vs has been attained for inversion-type MOSFETs fabricated on 4H-SiC(0001)Si and (000-1)C faces, respectively. The channel mobility shows a maximum when the increase of oxide thickness during N2O annealing is approximately 5 nm. A lateral RESURF MOSFET with gate oxides formed by the proposed process has blocked 1450 V and showed a low on-resistance of 75 mcm2, which is one of the best performances among lateral SiC MOSFETs reported.


2003 ◽  
Vol 765 ◽  
Author(s):  
K. Choi ◽  
H. Harris ◽  
S. Gangopadhyay ◽  
H. Temkin

AbstractA cleaning process resulting in atomically smooth, hydrogen-terminated, silicon surface that would inhibit formation of native silicon oxide is needed for high-k gate dielectric deposition. Various cleaning methods thus need to be tested in terms of resistance to native oxide formation. Native oxide re-growth is studied as a function of exposure time to atmospheric ambient using ellipsometry. Hafnium dioxide film (k ~23) is deposited on the as-cleaned substrates by electron beam evaporation and subsequently annealed in hydrogen. The difference in the effective oxide thickness re-grown on surfaces treated with the conventional RCA and modified Shiraki cleaning methods, after one-hour exposure, can be as large as 2 Å. This is significant in device applications demanding equivalent oxide thickness less than 20 Å. The degree of hydrogen passivation, surface micro-roughness and organic removal capability are considered to be the main factors that explain the differences between the cleaning methods. Data derived from capacitance-voltage analysis of test capacitors verified the trend observed in the native oxide thickness measurements. An increase of 10~15 % in accumulation capacitance is observed in the samples treated by the new cleaning method.


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