The dependence of channel length on channel width in narrow-channel CMOS devices for 0.35-0.13 μm technologies

2000 ◽  
Vol 21 (2) ◽  
pp. 85-87 ◽  
Author(s):  
T.B. Hook ◽  
S. Biesemans ◽  
J. Slinkman
Keyword(s):  
Narrow Channel ◽  
Channel Length ◽  
Channel Width

Dependence of hot-carrier immunity on channel length and channel width in MOSFETs with N/sub 2/O-grown gate oxides

1992 ◽  
Vol 13 (12) ◽  
pp. 651-653 ◽  
Author(s):  
G.Q. Lo ◽  
J. Ahn ◽  
D.-L. Kwong ◽  
K.K. Young
Keyword(s):  
Channel Length ◽  
Channel Width ◽  
Gate Oxides ◽  
Hot Carrier

Design and Gate Drive Considerations for Epitaxial 1.2 kV Buried Grid N-on and N-off JFETs for Operation at 250°C

2010 ◽  
Vol 645-648 ◽  
pp. 961-964 ◽  
Author(s):  
Jang Kwon Lim ◽  
Mietek Bakowski ◽  
Hans Peter Nee
Keyword(s):  
Threshold Voltage ◽  
Doping Concentration ◽  
Channel Length ◽  
Channel Width ◽  
Temperature Range ◽  
Turn On ◽  
Switching Losses ◽  
Order Of Magnitude ◽  
Gate Resistance

The 1.2 kV 4H-SiC buried-grid vertical JFET structures with Normally-on (N-on) and Normally-off (N-off) design were investigated by simulations. The conduction and switching properties were determined in the temperature range from -50°C to 250°C. In this paper, the characteristics of the N-on designs with threshold voltage (Vth) of -50 V and -10 V are compared with the N-off design (Vth=0). The presented data are for devices with the same channel length at 250°C. The results show that the on-resistance (Ron) decreases with increasing channel doping concentration and decreasing channel width. The presented turn-on, Eon, and turn-off, Eoff, energies per pulse are calculated under the switching conditions 100 A/cm2 and 600 V with a gate resistance of Rg=1 . For the two N-on designs the total switching losses, Esw=Eon+Eoff, differ less than 30% with Wch 0.7 m. With Wch=0.5 m the switching losses of N-off design are almost one order of magnitude higher than those of the N-on design with Vth = -50 V.

A New Mismatch Model of Temperature and Narrow Channel Width Dependence on Threshold Voltage of MOSFETs

2014 ◽  
Vol 931-932 ◽  
pp. 984-988
Author(s):  
Anucha Ruangphanit ◽  
Natthaphon Sakuna ◽  
Surasak Niemcharoen ◽  
Rangson Muanghlua
Keyword(s):  
Threshold Voltage ◽  
Narrow Channel ◽  
Channel Width

scholarly journals Towards an Optimal Pressure Tap Design for Fluid-Flow Characterisation at Microscales

Materials ◽  
2019 ◽  
Vol 12 (7) ◽  
pp. 1086 ◽  
Author(s):  
Tomás Rodrigues ◽  
Francisco Galindo-Rosales ◽  
Laura Campo-Deaño
Keyword(s):  
Pressure Drop ◽  
Soft Lithography ◽  
Rectangular Channel ◽  
Fluid Pressure ◽  
Pressure Sensors ◽  
Optimal Solution ◽  
Channel Length ◽  
Creeping Flow ◽  
Channel Width ◽  
Test Fluid

Measuring fluid pressure in microchannels is difficult and constitutes a challenge to even the most experienced of experimentalists. Currently, to the best of the authors’ knowledge, no optimal solution are being used for the design of pressure taps, nor guidelines concerning their shape and its relation with the accuracy of the readings. In an attempt to address this issue, a parametric study was devised to evaluate the performance of different pressure tap designs, 18 in total. These were obtained by combining three shape parameters: sub-channel width (w) and sub-channel–tap radius (R) or angle (α), while having the sub-channel length kept constant. For each configuration, pressure drop measurements were carried out along several lengths of a straight microfluidic rectangular channel and later compared to an analytical solution. The microchannels were fabricated out of PDMS using standard soft-lithography techniques, pressure drop was measured with differential pressure sensors, the test fluid was DI water and the flow conditions varied from creeping flow up to R e c ∼100. Pressure taps, having smooth contours (characterised by the radius R) and a sub-channel width (w) of 108 μ m , performed the best with results from that of radius R = 50 μ m only falling short of the theory by a mere ∼ 5 % .

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

2021 ◽  
Author(s):  
Kuleen Kumar ◽  
Rudra Sankar Dhar
Keyword(s):  
Ballistic Transport ◽  
Drain Current ◽  
Narrow Channel ◽  
Channel Length ◽  
Charge Carriers ◽  
Double Gate ◽  
Major Objective ◽  
Maximum Charge ◽  
Microelectronic Technology ◽  
Intervalley Scattering

Abstract The strain silicon technology with FET is a dominant technology providing enrichment in carrier velocity in nanoscaled device by change of band structure arrangement. Leakage reduction while enhancement in drain current is another major objective therefore, designing a nano-regime double gate FET with strained channel is perceived. So, design and implementation of a double gate strained heterostructure on insulator (DG-SHOI) FET with tri-layered channel (s-Si/s-SiGe/s-Si) is the core. Biaxial strain is created in channel by inculcating three layers with optimal thicknesses while narrow channel depletion regions are strongly controlled by equipotential gates. Consequently, maximum charge carriers accumulate in channel due to quantum carrier confinement instigating ballistic transport across the 22 nm channel length device leading to lessening of intervalley scattering. In comparison to existing 22 nm DGSOI FET, drain current augmentation of 56% and transconductance amplification of 87.6% is observed while DIBL is prudently reduced for this newly designed and implemented DG-SHOI FET, signifying advancement in microelectronic technology.

Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices

2018 ◽  
Vol 3 (2) ◽  
Author(s):  
Shen-Li Chen ◽  
Chun-Ju Lin ◽  
Huang Yu-Ting
Keyword(s):  
Metal Oxide ◽  
High Voltage ◽  
Electrostatic Discharge ◽  
Complementary Metal Oxide Semiconductor ◽  
Narrow Channel ◽  
Metal Oxide Semiconductor ◽  
Channel Width ◽  
Oxide Semiconductor ◽  
Drain Side ◽  
Better Than

Abstract How to effectively enhance the reliability robustness in high-voltage (HV) BCD [(bipolar) complementary metal-oxide semiconductor (CMOS) diffusion metaloxide semiconductor (DMOS)] processes is an important issue. Influences of layouttype dependences on anti-electrostatic discharge (ESD) robustness in a 0.25-μm 60-V process will be studied in this chapter, which includes, in part (1), the traditional striped-type n-channel lateral-diffused MOSFET (nLDMOS), waffle-type nLDMOS, and nLDMOS embedded with a “p-n-p”-arranged silicon-controlled rectifier (SCR) devices in the drain side; and in part (2) a p-channel LDMOS (pLDMOS) with an embedded “p-n-p-n-p”-arranged-type SCR in the drain side (diffusion regions of the drain side is P+-N+-P+-N+-P+). Then, these LDMOS devices are used to evaluate the influence of layout architecture on trigger voltage (Vt1), holding voltage (Vh), and secondary breakdown current (It2). Eventually, the sketching of the layout pattern of a HV LDMOS is a very important issue in the anti-ESD consideration. Also, in part (1), the waffle-type nLDMOS DUT contributes poorly to It2 robustness due to the non-uniform turned-on phenomenon and a narrow channel width per unit finger. Therefore, the It2 robustness of a waffle-type nLDMOS device is decreased about 17% as compared to a traditional striped-type nLDMOS device (reference DUT-1). The ESD abilities of traditional stripedtype and waffle-type nLDMOS devices with an embedded SCR (“p-n-p”-manner arrangement in the drain side) are better than a traditional nLDMOS 224.4% in average. Noteworthy, the nLDMOS-SCR with the “p-n-p” -arranged-type in the drainend is a good structure for the anti-ESD reliability especially in HV usages. Furthermore, in part (2) this layout manner of P+ discrete-island distributions in the drain-side have some impacts on the anti-ESD and anti-latch-up (LU) immunities. All of their It2 values have reached above 6 A; however, the major repercussion is that the Vh value will be decreased about 66.7 ~ 73.7%.

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