Three-dimensional self-consistent simulation of silicon quantum-dot floating-gate flash memory device

1999 ◽  
Vol 20 (6) ◽  
pp. 286-288 ◽  
Author(s):  
A. Thean ◽  
J.P. Leburton
Keyword(s):  
Quantum Dot ◽  
Flash Memory ◽  
Three Dimensional ◽  
Memory Device ◽  
Floating Gate ◽  
Silicon Quantum Dot ◽  
Self Consistent

SELF-CONSISTENT SIMULATION OF QUANTUM DOT FLASH MEMORY DEVICE WITH SiO2 AND HfO2 DIELECTRICS

2005 ◽  
Vol 04 (02) ◽  
pp. 171-178
Author(s):  
CHEE CHING CHONG ◽  
KAI HONG ZHOU ◽  
PING BAI ◽  
ER PING LI ◽  
GANESH S. SAMUDRA
Keyword(s):  
Quantum Dot ◽  
Flash Memory ◽  
Gate Dielectric ◽  
Tunneling Current ◽  
Memory Device ◽  
Device Structure ◽  
Dielectric Thickness ◽  
Silicon Quantum Dot ◽  
High K ◽  
Self Consistent

Flash memory structure in which a silicon quantum dot embedded in the gate dielectric region between the channel and the control gate is considered. A self-consistent simulation for such memory devices is performed and aims to understand the relationship between the device structure and the meaningful quantities, as required for an efficient device operation. In this study, both the traditional SiO2 and HfO2 high-k dielectrics are being explored, and their results are compared and contrasted. In particular, the superiority of HfO2 over the SiO2 is demonstrated through various interlocking investigations on the relationships between the tunneling current, dielectric thickness, barrier height, programming and retention times.

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

2019 ◽  
Author(s):  
Jun Hirota ◽  
Ken Hoshino ◽  
Tsukasa Nakai ◽  
Kohei Yamasue ◽  
Yasuo Cho
Keyword(s):  
Spatial Resolution ◽  
Flash Memory ◽  
Analytical Techniques ◽  
Memory Cell ◽  
Memory Device ◽  
Floating Gate ◽  
Order Structure ◽  
Carrier Distribution ◽  
Nonlinear Dielectric ◽  
Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Threshold Voltage Shift in Hetero-nanocystal Floating Gate Flash Memory

2004 ◽  
Vol 832 ◽  
Author(s):  
Yan Zhu ◽  
Dengtao Zhao ◽  
Ruigang Li ◽  
Jianlin Liu
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Oxide Thickness ◽  
Memory Device ◽  
Floating Gate ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Poisson Boltzmann ◽  
Poisson Boltzmann Equation ◽  
Dot Density

ABSTRACTThe threshold voltage shift of a p-channel Ge/Si hetero-nanocrystal floating gate memory device was investigated both numerically and phenomenologically. The numerical investigations, by solving 2-D Poisson-Boltzmann equation, show that the presence of the Ge on Si dot tremendously prolongs the retention time, reflected by the time decay behavior of the threshold voltage shift. The increase of the thickness of either Si or Ge dot will reduce the threshold voltage shift. The shift strongly depends on the dot density. Nevertheless, only a weak relation between the threshold voltage shift and the tunneling oxide thickness was found. A circuit model was then introduced to interpret the behavior of threshold voltage shift, which agrees well with the results of the numerical method.

Memory Operation of Silicon Quantum-Dot Floating-Gate Metal-Oxide-Semiconductor Field-Effect Transistors

2001 ◽  
Vol 40 (Part 2, No. 7B) ◽  
pp. L721-L723 ◽  
Author(s):  
Atsushi Kohno ◽  
Hideki Murakami ◽  
Mitsuhisa Ikeda ◽  
Seiichi Miyazaki ◽  
Masataka Hirose
Keyword(s):  
Quantum Dot ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Silicon Quantum Dot

CARBON NANOTUBE BASED NONVOLATILE MEMORY DEVICES

2006 ◽  
Vol 16 (04) ◽  
pp. 959-975 ◽  
Author(s):  
YUEGANG ZHANG
Keyword(s):  
Carbon Nanotube ◽  
Flash Memory ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Memory Device ◽  
Floating Gate ◽  
Memory Devices ◽  
Memory Cells ◽  
Nonvolatile Memory Devices ◽  
Electrostatic Coupling

The technology progress and increasing high density demand have driven the nonvolatile memory devices into nanometer scale region. There is an urgent need of new materials to address the high programming voltage and current leakage problems in the current flash memory devices. As one of the most important nanomaterials with excellent mechanical and electronic properties, carbon nanotube has been explored for various nonvolatile memory applications. While earlier proposals of "bucky shuttle" memories and nanoelectromechanical memories remain as concepts due to fabrication difficulty, recent studies have experimentally demonstrated various prototypes of nonvolatile memory cells based on nanotube field-effect-transistor and discrete charge storage bits, which include nano-floating gate memory cells using metal nanocrystals, oxide-nitride-oxide memory stack, and more simpler trap-in-oxide memory devices. Despite of the very limited research results, distinct advantages of high charging efficiency at low operation voltage has been demonstrated. Single-electron charging effect has been observed in the nanotube memory device with quantum dot floating gates. The good memory performance even with primitive memory cells is attributed to the excellent electrostatic coupling of the unique one-dimensional nanotube channel with the floating gate and the control gate, which gives extraordinary charge sensibility and high current injection efficiency. Further improvement is expected on the retention time at room temperature and programming speed if the most advanced fabrication technology were used to make the nanotube based memory cells.

Two-dimensional self-consistent simulation of a triangular p-channel SOI nano-flash memory device

2002 ◽  
Vol 49 (8) ◽  
pp. 1420-1426 ◽  
Author(s):  
Xiaohui Tang ◽  
X. Baie ◽  
J.-P. Colinge ◽  
C. Gustin ◽  
V. Bayot
Keyword(s):  
Flash Memory ◽  
Memory Device ◽  
Two Dimensional ◽  
Self Consistent

Multi-Bit Quantum Dot Nonvolatile Memory (QDNVM) Using Cladded Germanium and Silicon Quantum Dots

2015 ◽  
Vol 24 (03n04) ◽  
pp. 1550003 ◽  
Author(s):  
Murali Lingalugari ◽  
Pik-Yiu Chan ◽  
Evan Heller ◽  
Faquir Jain
Keyword(s):  
Quantum Dots ◽  
Quantum Dot ◽  
Nonvolatile Memory ◽  
Complementary Metal Oxide Semiconductor ◽  
Memory Device ◽  
Floating Gate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Device Structure ◽  
Nonvolatile Memory Device

In this paper, we are experimentally demonstrating the multi-bit storage of a nonvolatile memory device with cladded quantum dots as the floating gate. These quantum dot nonvolatile memory (QDNVM) devices were fabricated by using standard complementary metal-oxide-semiconductor (CMOS) process. The quantum dots in the floating gate region assembled using site-specific selfassembly (SSA) technique. Quantum mechanical simulations of this device structure are also presented. The experimental results show that the voltage separation between the bits was 0.15V and the voltage pulses required to write these bits were 11.7V and 30V. These devices demonstrated the larger write voltage separation between the bits.

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