High-speed performance of 0.35 μm CMOS gates fabricated on low-dose SIMOX substrates with/without an N-well underneath the buried oxide layer

1996 ◽  
Vol 17 (3) ◽  
pp. 106-108 ◽  
Author(s):  
A. Yoshino ◽  
K. Kumagai ◽  
N. Hamatake ◽  
T. Tatsumi ◽  
H. Onishi ◽  
...  
2004 ◽  
Vol 36 (8) ◽  
pp. 945-948 ◽  
Author(s):  
A. Jaroenworaluck ◽  
P. Sarmphim ◽  
S. Muensit ◽  
R. Stevens

2002 ◽  
Vol 158-159 ◽  
pp. 180-185
Author(s):  
Xiang Wang ◽  
Meng Chen ◽  
Yemin Dong ◽  
Jing Chen ◽  
Xi Wang ◽  
...  

Author(s):  
M. Sudou ◽  
M. Kainuma ◽  
K. Arai ◽  
M. Takamatsu ◽  
T. Nakai ◽  
...  
Keyword(s):  
Low Dose ◽  

Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.


Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.


2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.


2021 ◽  
Vol 1045 (1) ◽  
pp. 012040
Author(s):  
Fahim Faisal ◽  
Mirza Muntasir Nishat ◽  
Sayka Afreen Mim ◽  
Hafsa Akter ◽  
Md. Rafid Kaysar Shagor
Keyword(s):  

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