A low cost and high current gain a-Si/c-Si heterojunction photoreceiver for large area optoelectronics integrated circuit applications

1995 ◽  
Vol 16 (5) ◽  
pp. 190-192 ◽  
Author(s):  
Y.K. Fang ◽  
C.R. Liu ◽  
K.H. Chen ◽  
C.H. Lin
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Current Gain ◽  
High Current ◽  
Large Area

scholarly journals Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration

Micromachines ◽  
2019 ◽  
Vol 10 (5) ◽  
pp. 342 ◽  
Author(s):  
Tanja Braun ◽  
Karl-Friedrich Becker ◽  
Ole Hoelck ◽  
Steve Voges ◽  
Ruben Kahle ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Low Cost ◽  
Form Factors ◽  
Heterogeneous Integration ◽  
Passive Component ◽  
Wafer Level ◽  
Large Area ◽  
Component Integration ◽  
Application Specific Integrated Circuit ◽  
Power Management Unit

Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.

1600 V, 5.1 mΩ●cm2 4H-SiC BJT with a High Current Gain of β=70

2008 ◽  
Vol 600-603 ◽  
pp. 1155-1158 ◽  
Author(s):  
Jian Hui Zhang ◽  
Petre Alexandrov ◽  
Jian Hui Zhao
Keyword(s):  
High Performance ◽  
Voltage Drop ◽  
High Gain ◽  
Current Gain ◽  
High Current ◽  
Large Area ◽  
Collector Current ◽  
Forward Voltage Drop ◽  
Ac Current ◽  
Dc Current

This paper reports a newly achieved best result on the common emitter current gain of 4H-SiC high power bipolar junction transistors (BJTs). A fabricated 1600 V – 15 A 4H-SiC power BJT with an active area of 1.7 mm2 shows a high DC current gain (b) of 70, when it conducts 9.8 A collector current at a base current of only 140 mA. The maximum AC current gain (DIC/DIB) is up to 78. This high performance BJT has an open base collector-to-emitter blocking voltage (VCEO) of over 1674 V with a leakage current of 1.6 μA, and a specific on-resistance (RSP-ON) of 5.1 mW.cm2 when it conducts 7.0 A (412 A/cm2) at a forward voltage drop of VCE = 2.1 V. A large area 4H-SiC BJT with a footprint of 4.1 mm x 4.1 mm has also shown a DC current gain over 50. These high-gain, high-voltage and high-current 4H-SiC BJTs further support a promising future for 4H-SiC BJT applications.

InGaP/GaAs pnp Heterojunction Bipolar Transistor with δ-Doped Sheet between Base-Emitter Junction

2008 ◽  
Vol 47-50 ◽  
pp. 383-386
Author(s):  
Jung Hui Tsai ◽  
Shao Yen Chiu ◽  
Wen Shiung Lour ◽  
Chien Ming Li ◽  
Yi Zhen Wu ◽  
...  
Keyword(s):  
Valence Band ◽  
Integrated Circuit ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
Current Gain ◽  
High Current ◽  
Offset Voltage ◽  
Potential Spike ◽  
Emitter Junction ◽  
Valence Band Discontinuity

In this article, a novel InGaP/GaAs pnp δ-doped heterojunction bipolar transistor is first demonstrated. Though the valence band discontinuity at InGaP/GaAs heterojunction is relatively large, the addition of a δ-doped sheet between two spacer layers at the emitter-base junction effectively eliminates the potential spike and increases the confined barrier for electrons, simultaneously. Experimentally, a high current gain of 25 and an offset voltage of 100 mV are achieved. The offset voltage is much smaller than the conventional InGaP/GaAs pnp HBT. The proposed device could be used for linear amplifiers and low-power complementary integrated circuit applications.

Computer simulation study about the dependence of amorphous silicon photonic waveguides efficiency on the material quality

2020 ◽  
Vol 90 (3) ◽  
pp. 30502
Author(s):  
Alessandro Fantoni ◽  
João Costa ◽  
Paulo Lourenço ◽  
Manuela Vieira
Keyword(s):  
Amorphous Silicon ◽  
High Throughput Screening ◽  
Simulation Analysis ◽  
Low Cost ◽  
Deposition Process ◽  
Large Area ◽  
Sidewall Roughness ◽  
Sensing Applications ◽  
Fabrication Defects ◽  
The Impact

Amorphous silicon PECVD photonic integrated devices are promising candidates for low cost sensing applications. This manuscript reports a simulation analysis about the impact on the overall efficiency caused by the lithography imperfections in the deposition process. The tolerance to the fabrication defects of a photonic sensor based on surface plasmonic resonance is analysed. The simulations are performed with FDTD and BPM algorithms. The device is a plasmonic interferometer composed by an a-Si:H waveguide covered by a thin gold layer. The sensing analysis is performed by equally splitting the input light into two arms, allowing the sensor to be calibrated by its reference arm. Two different 1 × 2 power splitter configurations are presented: a directional coupler and a multimode interference splitter. The waveguide sidewall roughness is considered as the major negative effect caused by deposition imperfections. The simulation results show that plasmonic effects can be excited in the interferometric waveguide structure, allowing a sensing device with enough sensitivity to support the functioning of a bio sensor for high throughput screening. In addition, the good tolerance to the waveguide wall roughness, points out the PECVD deposition technique as reliable method for the overall sensor system to be produced in a low-cost system. The large area deposition of photonics structures, allowed by the PECVD method, can be explored to design a multiplexed system for analysis of multiple biomarkers to further increase the tolerance to fabrication defects.

Programmable Integrated Photonics

2020 ◽  
Author(s):  
José Capmany ◽  
Daniel Pérez
Keyword(s):  
Integrated Circuit ◽  
Performance Monitoring ◽  
Low Cost ◽  
Limiting Factors ◽  
External Control ◽  
Integrated Photonics ◽  
New Paradigm ◽  
Photonic Integrated Circuit ◽  
And Performance ◽  
Application Fields

Programmable Integrated Photonics (PIP) is a new paradigm that aims at designing common integrated optical hardware configurations, which by suitable programming can implement a variety of functionalities that, in turn, can be exploited as basic operations in many application fields. Programmability enables by means of external control signals both chip reconfiguration for multifunction operation as well as chip stabilization against non-ideal operation due to fluctuations in environmental conditions and fabrication errors. Programming also allows activating parts of the chip, which are not essential for the implementation of a given functionality but can be of help in reducing noise levels through the diversion of undesired reflections. After some years where the Application Specific Photonic Integrated Circuit (ASPIC) paradigm has completely dominated the field of integrated optics, there is an increasing interest in PIP justified by the surge of a number of emerging applications that are and will be calling for true flexibility, reconfigurability as well as low-cost, compact and low-power consuming devices. This book aims to provide a comprehensive introduction to this emergent field covering aspects that range from the basic aspects of technologies and building photonic component blocks to the design alternatives and principles of complex programmable photonics circuits, their limiting factors, techniques for characterization and performance monitoring/control and their salient applications both in the classical as well as in the quantum information fields. The book concentrates and focuses mainly on the distinctive features of programmable photonics as compared to more traditional ASPIC approaches.

A novel low cost texturization method for large area commercial mono-crystalline silicon solar cells

2006 ◽  
Vol 90 (20) ◽  
pp. 3557-3567 ◽  
Author(s):  
U. Gangopadhyay ◽  
K.H. Kim ◽  
S.K. Dhungel ◽  
U. Manna ◽  
P.K. Basu ◽  
...  
Keyword(s):  
Solar Cells ◽  
Crystalline Silicon ◽  
Low Cost ◽  
Silicon Solar Cells ◽  
Large Area ◽  
Crystalline Silicon Solar Cells

scholarly journals Superhydrophobicity and Durability in Recyclable Polymers Coating

2021 ◽  
Vol 13 (15) ◽  
pp. 8244
Author(s):  
Francesca Cirisano ◽  
Michele Ferrari
Keyword(s):  
Thermal Treatment ◽  
Superhydrophobic Surface ◽  
Low Cost ◽  
Spray Coating ◽  
Large Area ◽  
Average Roughness ◽  
Water Contact ◽  
Alkaline Environments ◽  
Fine Control ◽  
Recycle And Reuse

Highly hydrophobic and superhydrophobic materials obtained from recycled polymers represent an interesting challenge to recycle and reuse advanced performance materials after their first life. In this article, we present a simple and low-cost method to fabricate a superhydrophobic surface by employing polytetrafluoroethylene (PTFE) powder in polystyrene (PS) dispersion. With respect to the literature, the superhydrophobic surface (SHS) was prepared by utilizing a spray- coating technique at room temperature, a glass substrate without any further modification or thermal treatment, and which can be applied onto a large area and on to any type of material with some degree of fine control over the wettability properties. The prepared surface showed superhydrophobic behavior with a water contact angle (CA) of 170°; furthermore, the coating was characterized with different techniques, such as a 3D confocal profilometer, to measure the average roughness of the coating, and scanning electron microscopy (SEM) to characterize the surface morphology. In addition, the durability of SH coating was investigated by a long-water impact test (raining test), thermal treatment at high temperature, an abrasion test, and in acidic and alkaline environments. The present study may suggest an easy and scalable method to produce SHS PS/PTFE films that may find implementation in various fields.

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