High-frequency InP/InGaAs double heterojunction bipolar transistors on Si substrate

1993 ◽  
Vol 14 (7) ◽  
pp. 357-359 ◽  
Author(s):  
Y. Matsuoka ◽  
K. Kurishima ◽  
T. Makimoto
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
High Frequency ◽  
Bipolar Transistors ◽  
Si Substrate ◽  
Double Heterojunction

17 Gbit/s pin-PD/decision circuit using InP/InGaAs double-heterojunction bipolar transistors

1996 ◽  
Vol 32 (4) ◽  
pp. 393 ◽  
Author(s):  
M. Yoneyama ◽  
E. Sano ◽  
S. Yamahata ◽  
Y. Matsuoka ◽  
M. Yaita
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Bipolar Transistors ◽  
Double Heterojunction ◽  
Decision Circuit

scholarly journals Performance prediction of InP/GaAsSb double heterojunction bipolar transistors for THz applications

2021 ◽  
Vol 130 (3) ◽  
pp. 034502
Author(s):  
Xin Wen ◽  
Akshay Arabhavi ◽  
Wei Quan ◽  
Olivier Ostinelli ◽  
Chhandak Mukherjee ◽  
...  
Keyword(s):  
Performance Prediction ◽  
Heterojunction Bipolar Transistors ◽  
Bipolar Transistors ◽  
Double Heterojunction ◽  
Thz Applications

Surface Leakage in GaN/InGaN Double Heterojunction Bipolar Transistors

2009 ◽  
Vol 30 (11) ◽  
pp. 1119-1121 ◽  
Author(s):  
Shyh-Chiang Shen ◽  
Yi-Che Lee ◽  
Hee-Jin Kim ◽  
Yun Zhang ◽  
Suk Choi ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Bipolar Transistors ◽  
Double Heterojunction ◽  
Surface Leakage

Prevention of InP/InGaAs/InP Double Heterojunction Bipolar Transistors from Current Gain Reduction during Passivation

2004 ◽  
Vol 833 ◽  
Author(s):  
Byoung-Gue Min ◽  
Jong-Min Lee ◽  
Seong-Il Kim ◽  
Chul-Won Ju ◽  
Kyung-Ho Lee
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Silicon Oxide ◽  
Surface Recombination ◽  
Surface States ◽  
Bipolar Transistors ◽  
Base Layer ◽  
Current Gain ◽  
Device Structure ◽  
Double Heterojunction ◽  
Gain Reduction

ABSTRACTA significant degradation of current gain of InP/InGaAs/InP double heterojunction bipolar transistors was observed after passivation. The amount of degradation depended on the degree of surface exposure of the p-type InGaAs base layer according to the epi-structure and device structure. The deposition conditions such as deposition temperature, kinds of materials (silicon oxide, silicon nitride and aluminum oxide) and film thickness were not major variables to affect the device performance. The gain reduction was prevented by the BOE treatment before the passivation. A possible explanation of this behavior is that unstable non-stoichiometric surface states produced by excess In, Ga, or As after mesa etching are eliminated by BOE treatment and reduce the surface recombination sites.

SiGe Heteroepitaxy for High Frequency Circuits

1998 ◽  
Vol 525 ◽  
Author(s):  
B. Tillack ◽  
D. Bolze ◽  
G. Fischer ◽  
G. Kissinger ◽  
D. Knoll ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
High Frequency ◽  
Defect Density ◽  
Process Capability ◽  
Chemical Vapor ◽  
Bipolar Transistors ◽  
Capability Indices ◽  
Data Points ◽  
B Doping ◽  
The Stability

ABSTRACTWe have determined the process capability of Low Pressure (Rapid Thermal) Chemical Vapor Deposition (LP(RT)CVD) of epitaxial Si/SiGe/Si stacks for heterojunction bipolar transistors (HIBTs). The transistor parameters primarily influenced by the epitaxial characteristics were measured for 600 identically processed 4” wafers. The results demonstrate that it is possible to control accurately the epitaxial process for a 25 nm thick graded SiGe base profile with 20 % Ge and very narrow B doping (5 nm). The pipe limited device yield of about 90 % for an emitter area of 104 μm2 indicates a very low defect density in the epitaxial layer stack. The process capability indices determined from about 40,000 data points demonstrate the stability and capability of the LP(RT)CVD epitaxy with regard to manufacturing requirements.

Sign in / Sign up

Export Citation Format

Share Document