A GaAsMISFET using an MBE-grown CaF/sub 2/ gate insulator layer

1988 ◽  
Vol 9 (10) ◽  
pp. 548-549 ◽  
Author(s):  
T. Waho ◽  
F. Yanagawa
Keyword(s):  
Gate Insulator ◽  
Insulator Layer

Study of Transport Through Low-Temperature GaAs Surface Insulator Layers

1991 ◽  
Vol 241 ◽  
Author(s):  
J. P. Ibbetson ◽  
L.-W. Yin ◽  
M. Hashemi ◽  
A. C. Gossard ◽  
U. K. Mishra
Keyword(s):  
Material Properties ◽  
Surface Effect ◽  
Thin Layers ◽  
Gate Insulator ◽  
High Resistivity ◽  
Growth Surface ◽  
Insulator Layer ◽  
Insulator Layers ◽  
Low Temperature Gaas ◽  
Effective Buffer

ABSTRACTSince epilayers of GaAs grown at low substrate temperature (LTGaAs) and annealed at 600°C were first demonstrated to be an effective buffer layer for eliminating backgating effects, the material properties and electronic characteristics of bulk LTGaAs have been actively investigated. Less attention has been paid to thin layers of LTGaAs (∼2000Å), although these have been shown to improve gate-to-drain breakdown characteristics when incorporated as the surface insulator layer in GaAs MISFET's. In bulk LTGaAs that has been annealed for 10 minutes at 600°C, the formation of arsenic precipitates with a density of 1018 cm-3 has been observed. These are considered to be at least partially responsible for the high resistivity of LTGaAs2. While the exact mechanism of precipitate formation is currently unknown, it would seem reasonable to expect the availability of the growth surface to have a significant effect on any defect redistribution during the anneal. This surface effect would become increasingly apparent as the LTGaAs layer thickness was decreased. It is desirable for MISFET applications that the LTGaAs gate insulator layer be as thin as possible, whilst maintaining high breakdown, in order to maximize device transconductance. To achieve this, it is important to understand how the observed bulk features (such as ∼60Å size arsenic precipitates) are affected in thin LTGaAs layers

Recessed-Gate GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistor Using a Dual Gate-Insulator Employing TiO2/SiN

2020 ◽  
Vol 20 (8) ◽  
pp. 4678-4683
Author(s):  
Jun Hyeok Jung ◽  
Min Su Cho ◽  
Won Douk Jang ◽  
Sang Ho Lee ◽  
Jaewon Jang ◽  
...  
Keyword(s):  
Electron Mobility ◽  
High Electron Mobility Transistor ◽  
Gate Insulator ◽  
High Electron ◽  
Insulator Layer ◽  
Metal Insulator ◽  
High Electron Mobility ◽  
Metal Insulator Semiconductor ◽  
Dual Gate ◽  
Recessed Gate

In this work, we present a normally-off recessed-gate AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) using a TiO2/SiN dual gate-insulator. We analyzed the electrical characteristics of the proposed device and found that the dual gate-insulator device achieves higher on-state currents than the device using a SiN gate-insulator because the high-k insulator layer of the dual gate-insulator improves the gate-controllability. The device using a TiO2/SiN gate-insulator shows better gate leakage current characteristics than the device with only TiO2 gate-insulator because of the high quality SiN gate-insulator. Therefore, the device using a dual gate-insulator can overcome disadvantages of a device using only TiO2 gate-insulator. To better predict the power consumption and the switching speed, we simulated the specific on-resistance (Ron, sp) according to the gate-to-drain distance (LGD) using the two-dimensional ATLAS simulator. The proposed device exhibits a threshold voltage of 2.3 V, a maximum drain current of 556 mA/mm, a low Ron, sp of 1.45 mΩ·cm2, and a breakdown voltage of 631 V at an off-state current of 1 μA/mm with VGS = 0 V. We have confirmed that a normally-off recessed-gate AlGaN/GaN MIS-HEMT using a TiO2/SiN dual gate-insulator is a promising candidate for power electronic applications.

Triple-probe Atomic Force Microscope: Measuring a carbon nanotube/DNA MIS-FET

2002 ◽  
Vol 761 ◽  
Author(s):  
Kei Shimotani ◽  
Hiroyuki Watanabe ◽  
Chikara Manabe ◽  
Taishi Shigematsu ◽  
Masaaki Shimizu
Keyword(s):  
Carbon Nanotube ◽  
Atomic Force Microscope ◽  
Gate Insulator ◽  
Switching Behavior ◽  
Insulator Layer ◽  
Terminal Device ◽  
Atomic Force ◽  
Current Voltage ◽  
Dna Strands ◽  
Walled Carbon Nanotubes

ABSTRACTWe have constructed an advanced electric probing system, which is a triple-probe atomic force microscope (T-AFM). The T-AFM consists of “Nanotweezers” and an AFM with a carbon nanotube probe. Using this system, we fabricated a single-walled carbon nanotubes (SWNTs)/deoxyribonucleic acid (DNA) three-terminal device and measured the current-voltage (I-V) curves of this device. In this three-terminal device, DNA strands were entangled with the SWNT bundle, and behaved as a gate-insulator-layer. This three-terminal device worked as a metal-insulator-semiconductor field effect transistor (MIS-FET) with depletion switching behavior.

Triple-probe Atomic Force Microscope: Measuring a carbon nanotube/DNA MIS-FET

2002 ◽  
Vol 738 ◽  
Author(s):  
Kei Shimotani ◽  
Hiroyuki Watanabe ◽  
Chikara Manabe ◽  
Taishi Shigematsu ◽  
Masaaki Shimizu
Keyword(s):  
Carbon Nanotube ◽  
Atomic Force Microscope ◽  
Gate Insulator ◽  
Switching Behavior ◽  
Insulator Layer ◽  
Terminal Device ◽  
Atomic Force ◽  
Current Voltage ◽  
Dna Strands ◽  
Walled Carbon Nanotubes

ABSTRACTWe have constructed an advanced electric probing system, which is a triple-probe atomic force microscope (T-AFM). The T-AFM consists of “Nanotweezers” and an AFM with a carbon nanotube probe. Using this system, we fabricated a single-walled carbon nanotubes (SWNTs)/deoxyribonucleic acid (DNA) three-terminal device and measured the current-voltage (I-V) curves of this device. In this three-terminal device, DNA strands were entangled with the SWNT bundle, and behaved as a gate-insulator-layer. This three-terminal device worked as a metal-insulator-semiconductor field effect transistor (MIS-FET) with depletion switching behavior.

scholarly journals Effect of Coercive Voltage and Charge Injection on Performance of a Ferroelectric-Gate Thin-Film Transistor

2013 ◽  
Vol 2013 ◽  
pp. 1-8 ◽  
Author(s):  
P. T. Tue ◽  
T. Miyasako ◽  
E. Tokumitsu ◽  
T. Shimoda
Keyword(s):  
Thin Film ◽  
Indium Tin Oxide ◽  
Thin Film Transistor ◽  
Charge Injection ◽  
Memory Window ◽  
Gate Insulator ◽  
Insulator Layer ◽  
Capping Layer ◽  
Insulator Layers ◽  
Injection Effect

We adopted a lanthanum oxide capping layer between semiconducting channel and insulator layers for fabrication of a ferroelectric-gate thin-film transistor memory (FGT) which uses solution-processed indium-tin-oxide (ITO) and lead-zirconium-titanate (PZT) film as a channel layer and a gate insulator, respectively. Good transistor characteristics such as a high “on/off” current ratio, high channel mobility, and a large memory window of 108, 15.0 cm2 V−1 s−1, and 3.5 V were obtained, respectively. Further, a correlation between effective coercive voltage, charge injection effect, and FGT’s memory window was investigated. It is found that the charge injection from the channel to the insulator layer, which occurs at a high electric field, dramatically influences the memory window. The memory window’s enhancement can be explained by a dual effect of the capping layer: (1) a reduction of the charge injection and (2) an increase of effective coercive voltage dropped on the insulator.

Studies of the Stability of Amorphous Silicon Thin Film Transistors

1992 ◽  
Vol 258 ◽  
Author(s):  
T. Globus ◽  
M. Shur ◽  
M. Hack
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Experimental Studies ◽  
Gate Insulator ◽  
Localized States ◽  
Silicon Thin Film ◽  
Insulator Layer ◽  
Voltage Stress

ABSTRACTOur experimental studies confirm that changes in a-Si Thin Film Transistors (TFTs) under voltage stress occur in the device channel and not in the contacts. We demonstrate that stressing an a-Si TFT not only shifts the device threshold voltage but can also changes the slope of the semilog subthreshold current dependence on the gate voltage. In addition, stressing can decrease the minimum leakage current. The creation of new localized states in the amorphous silicon under voltage stress qualitatively explains all these effects, while carrier tunneling and trapping in the gate insulator layer cannot by itself explain our data. At large negative gate voltages, the leakage current increases due to the holes injected into the channel. This hole current is also affected by voltage stress as can be predicted by the state creation mechanism.

Electrical properties of charging effect in Au nanoparticle memory device

2009 ◽  
Vol 1207 ◽  
Author(s):  
Sung-Mok Jung ◽  
Hyung-Jun Kim ◽  
Bong-Jin Kim ◽  
Il Seo ◽  
Tae-Sik Yoon ◽  
...  
Keyword(s):  
Self Assembly ◽  
Memory Device ◽  
Gate Insulator ◽  
Electrical Performance ◽  
Au Nanoparticle ◽  
Charge Storage ◽  
Insulator Layer ◽  
Au Nps ◽  
Memory Applications ◽  
Charging Effect

AbstractSemiconductors or metal nanoparticles (NPs) using their monolayer bindings with self-assembly chemicals are an attractive topic for device researchers. Electrical performance of such structures can be investigated for a particular application, such as memory device. Currently, Au NPs has been reported to show a substantial potential in the memory applications. In this study, Au NP and gluing layer were fabricated through a new method of monolayer formation of a chemical bonding or gluing. In this study, a new NPs memory system was fabricated by using organic semiconductor, i.e., pentacene as the active layer, evaporated Au as electrode, SiO2 as the gate insulator layer on silicon wafer. In addition, Au NPs coated with binding chemicals were used as charge storage elements on an APTES (3-amino-propyltriethoxysilane) as a gluing layer. In order to investigate chemical binding of Au NP to the gate insulator layer, GPTMS (3-glycidoxy-propyltrimethoxysilane) were coated on the Au NPs. As a result of that, a layer of gold nanoparticles has been incorporated into a metal-pentacene-insulator-semiconductor (MPIS) structure. The MPIS device with the Au NP exhibited a hysteresis in its capacitance versus voltage analysis. Charge storage in the layer of nanoparticles is thought to be responsible for this effect.

scholarly journals Normally-off p-GaN Gated AlGaN/GaN MIS-HEMTs with ALD-Grown Al2O3/AlN Composite Gate Insulator

Membranes ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 727
Author(s):  
Hsien-Chin Chiu ◽  
Chia-Hao Liu ◽  
Chong-Rong Huang ◽  
Chi-Chuan Chiu ◽  
Hsiang-Chun Wang ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
High Reliability ◽  
Atomic Layer ◽  
High Electron Mobility Transistor ◽  
Gate Insulator ◽  
High Electron ◽  
Insulator Layer ◽  
Enhancement Mode ◽  
Layer Deposition ◽  
P Type

A metal–insulator–semiconductor p-type GaN gate high-electron-mobility transistor (MIS-HEMT) with an Al2O3/AlN gate insulator layer deposited through atomic layer deposition was investigated. A favorable interface was observed between the selected insulator, atomic layer deposition–grown AlN, and GaN. A conventional p-type enhancement-mode GaN device without an Al2O3/AlN layer, known as a Schottky gate (SG) p-GaN HEMT, was also fabricated for comparison. Because of the presence of the Al2O3/AlN layer, the gate leakage and threshold voltage of the MIS-HEMT improved more than those of the SG-HEMT did. Additionally, a high turn-on voltage was obtained. The MIS-HEMT was shown to be reliable with a long lifetime. Hence, growing a high-quality Al2O3/AlN layer in an HEMT can help realize a high-performance enhancement-mode transistor with high stability, a large gate swing region, and high reliability.

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