Failure analysis of high-density CMOS SRAMs: using realistic defect modeling and I/sub DDQ/ testing

1993 ◽  
Vol 10 (2) ◽  
pp. 13-23 ◽  
Author(s):  
S. Naik ◽  
F. Agricola ◽  
W. Maly
Keyword(s):  
Failure Analysis ◽  
High Density ◽  
Defect Modeling

Using the scanning electron microscope for failure analysis of high density magnetic media

1987 ◽  
Vol 45 ◽  
pp. 392-393
Author(s):  
Evelyn R. Ackerman ◽  
Gary D. Burnett
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Failure Analysis ◽  
High Density ◽  
Magnetic Media ◽  
Specific Data ◽  
Retrieval Systems ◽  
Operating Environments ◽  
The Media ◽  
Scanning Electron

Advancements in state of the art high density Head/Disk retrieval systems has increased the demand for sophisticated failure analysis methods. From 1968 to 1974 the emphasis was on the number of tracks per inch. (TPI) ranging from 100 to 400 as summarized in Table 1. This emphasis shifted with the increase in densities to include the number of bits per inch (BPI). A bit is formed by magnetizing the Fe203 particles of the media in one direction and allowing magnetic heads to recognize specific data patterns. From 1977 to 1986 the tracks per inch increased from 470 to 1400 corresponding to an increase from 6300 to 10,800 bits per inch respectively. Due to the reduction in the bit and track sizes, build and operating environments of systems have become critical factors in media reliability.Using the Ferrofluid pattern developing technique, the scanning electron microscope can be a valuable diagnostic tool in the examination of failure sites on disks.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Failure Analysis of High Density Polyethylene Butt Weld Joint

2011 ◽  
Vol 12 (2) ◽  
pp. 168-180 ◽  
Author(s):  
Fawad Tariq ◽  
Nausheen Naz ◽  
Muhammad Amir Khan ◽  
Rasheed Ahmed Baloch
Keyword(s):  
Failure Analysis ◽  
Weld Joint ◽  
High Density Polyethylene ◽  
High Density ◽  
Butt Weld

The Application of Novel Failure Analysis Techniques and Defect Modeling in Eliminating Short Poly End-Cap Problem in Submicron CMOS Devices

1996 ◽  
Author(s):  
Y.E. Hong ◽  
M.T.T. We
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Leakage Current ◽  
Packing Density ◽  
Process Change ◽  
Defect Modeling ◽  
Functional Failure ◽  
Analysis Techniques ◽  
Post Process ◽  
First Time

Abstract As transistor dimension shrinks down below submicron to cater for higher speed and higher packing density, it is very important to characterize the shrinkage carefully to avoid unwanted parametric problems. Leakage current across short poly end-cap is a new failure mechanism that falls in this category and was for the first time, uncovered in submicron multilayered CMOS devices. This mechanism was responsible for a systematic yield problem; identified as the 'centre wafer striping' functional failure problem. This paper presents the advanced failure analysis techniques and defect modeling used to narrow down and identify this new mechanism. Post process change by loosening the marginal poly end-cap criteria eliminated the problem completely.

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