Random access protocols for high-speed interprocessor communication based on an optical passive star topology

1991 ◽  
Vol 9 (6) ◽  
pp. 799-808 ◽  
Author(s):  
P.W. Dowd
Keyword(s):  
High Speed ◽  
Random Access ◽  
Interprocessor Communication ◽  
Star Topology ◽  
Access Protocols

Modern Random Access Protocols

2016 ◽  
Author(s):  
Matteo Berioli ◽  
Giuseppe Cocco ◽  
Gianluigi Liva ◽  
Andrea Munari
Keyword(s):  
Random Access ◽  
Access Protocols

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals A micromirror array with annular partitioning for high-speed random-access axial focusing

2020 ◽  
Vol 9 (1) ◽  
Author(s):  
Nathan Tessema Ersumo ◽  
Cem Yalcin ◽  
Nick Antipa ◽  
Nicolas Pégard ◽  
Laura Waller ◽  
...  
Keyword(s):  
Adaptive Optics ◽  
Visual Information ◽  
High Speed ◽  
Random Access ◽  
General Purpose ◽  
Phase Shifting ◽  
Optical Systems ◽  
Piston Motion ◽  
Refresh Rate ◽  
Circular Symmetry

Abstract Dynamic axial focusing functionality has recently experienced widespread incorporation in microscopy, augmented/virtual reality (AR/VR), adaptive optics and material processing. However, the limitations of existing varifocal tools continue to beset the performance capabilities and operating overhead of the optical systems that mobilize such functionality. The varifocal tools that are the least burdensome to operate (e.g. liquid crystal, elastomeric or optofluidic lenses) suffer from low (≈100 Hz) refresh rates. Conversely, the fastest devices sacrifice either critical capabilities such as their dwelling capacity (e.g. acoustic gradient lenses or monolithic micromechanical mirrors) or low operating overhead (e.g. deformable mirrors). Here, we present a general-purpose random-access axial focusing device that bridges these previously conflicting features of high speed, dwelling capacity and lightweight drive by employing low-rigidity micromirrors that exploit the robustness of defocusing phase profiles. Geometrically, the device consists of an 8.2 mm diameter array of piston-motion and 48-μm-pitch micromirror pixels that provide 2π phase shifting for wavelengths shorter than 1100 nm with 10–90% settling in 64.8 μs (i.e., 15.44 kHz refresh rate). The pixels are electrically partitioned into 32 rings for a driving scheme that enables phase-wrapped operation with circular symmetry and requires <30 V per channel. Optical experiments demonstrated the array’s wide focusing range with a measured ability to target 29 distinct resolvable depth planes. Overall, the features of the proposed array offer the potential for compact, straightforward methods of tackling bottlenecked applications, including high-throughput single-cell targeting in neurobiology and the delivery of dense 3D visual information in AR/VR.

Simulation and Design of a Silicon Nanowire based Phase Change Memory Cell

2012 ◽  
Vol 1431 ◽  
Author(s):  
Ramin Banan Sadeghian ◽  
Yusuf Leblebici ◽  
Ali Shakouri
Keyword(s):  
Phase Change ◽  
High Speed ◽  
Low Cost ◽  
Silicon Nanowire ◽  
Phase Change Memory ◽  
Random Access ◽  
Memory Cell ◽  
Oxide Thickness ◽  
Nanowire Diameter ◽  
Change Memory

ABSTRACTIn this work we present preliminary calculations and simulations to demonstrate feasibility of programming a nanoscale Phase Change Random Access Memory (PCRAM) cell by means of a silicon nanowire ballistic transistor (SNWBT). Memory cells based on ballistic transistors bear the advantage of having a small size and high-speed operation with low power requirements. A one-dimensional MOSFET model (FETToy) was used to estimate the output current of the nanowire as a function of its diameter. The gate oxide thickness was 1.5 nm, and the Fermi level at source was set to -0.32 eV. For the case of VDS = VGS = 1 V, when the nanowire diameter was increased from 1 to 60 nm, the output power density dropped from 109 to 106 W cm-2 , while the current increased from 20 to 90 μA. Finite element electro-thermal analysis were carried out on a segmented cylindrical phase-change memory cell made of Ge2Sb2Te5 (GST) chalcogenide, connected in series to the SNWBT. The diameter of the combined device, d, and the aspect ratio of the GST region were selected so as to achieve optimum heating of the GST. With the assumption that the bulk thermal conductivity of GST does not change significantly at the nanoscale, it was shown that for d = 24 nm, a ‘reset’ programming current of ID = 80 μA can heat the GST up to its melting point. The results presented herein can help in the design of low cost, high speed, and radiation tolerant nanoscale PCRAM devices.

Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

2021 ◽  
pp. 2150270
Author(s):  
Jitendra Kumar Mishra ◽  
Lakshmi Likhitha Mankali ◽  
Kavindra Kandpal ◽  
Prasanna Kumar Misra ◽  
Manish Goswami
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Static Noise Margin ◽  
Semiconductor Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

Sign in / Sign up

Export Citation Format

Share Document