Crosstalk measurements of integrated high-speed Ti:LiNbO/sub 3/ Delta beta -reversal switching circuits

Recentlly, high speed switching circuits using SiC power device have been developed for reduction of switching loss and downsizing of electric products. The high speed switching leads to the rapid changing of the drain voltage (dV/dt) during the switching period. This paper reports the effects of the dV/dt impact on the self-turn-on and the characteristics of SiC-MOSFET, especially the temperature dependence. The results shows that the gate bias voltage to suppress the self-turn-on is negatively correlated with the temperature. And it is also found that the dV/dt impact breaks down the gate source insulation and the dV/dt value to the breakdown is positively correlated with the temperature.

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A fast 10v diode quarter square multiplier

SIMULATION ◽

10.1177/003754976500500216 ◽

1965 ◽

Vol 5 (2) ◽

pp. 114-120

Author(s):

Robert H. Whigham

Keyword(s):

Phase Shift ◽

High Speed ◽

Dynamic Error ◽

Wide Band ◽

Thermal Drift ◽

Absolute Value ◽

Switching Circuits ◽

And Performance ◽

Shunt Series ◽

Differential Analyzer

This report describes the design and performance of a fast wideband quarter-square diode multiplier de signed to work with the ±10-v low-impedance com puting circuits of a high-speed iterative differential analyzer (ASTRAC II), or in other hybrid analog- digital computer systems. To reduce cost, the new multiplier employs absolute-value squaring circuits and does not require committed computer ampli fiers. Improved combination shunt-series switching circuits and low resistance values ensure wide band width (±0.5% of half-scale dynamic error at 10 Kc, <1 degree phase shift below 70 Kc). Temperature- compensating diodes in the bias networks reduce thermal drift below 0.7 mv/°C, so that the multiplier static accuracy of ±0.20% of half-scale is maintained from 15 to 40° C. A number of useful design hints are listed.

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Hybrid-Integrated Series-to-Parallel Converters for Gigabit Rates

ElectroComponent Science and Technology ◽

10.1155/apec.4.57 ◽

1977 ◽

Vol 4 (2) ◽

pp. 57-62 ◽

Cited By ~ 3

Author(s):

G. Hanke

Keyword(s):

Thick Film ◽

High Speed ◽

Conversion Ratio ◽

Linear Arrangement ◽

Switching Circuits ◽

High Bit Rates ◽

Strip Lines ◽

Data Signal ◽

Serial Mode ◽

Subnanosecond Range

The generation and processing of data signal sequences in the gigabit range make high demands on circuitry and technology. For this high-speed thick-film switching circuits have proved successful. With a suitable circuitry, which is tailored to both the requirements of the subnanosecond range and the conditions of the thick-film technique, it is possible to solve many problems connected with the generation and processing of data signals in the gigabit range.The conventional method of series-to-parallel conversion with shift registers can, however, not be applied at justifiable costs with the present-day components. Therefore signal processing at the receiving end by bit error rate measuring equipment at bit rates from 640 Mbit/s up to 1,28 Gbit/s is used to demonstrate hybrid-integrated thick-film circuits which, in connection with coaxial and strip lines, allow the series-to-parallel conversion of high bit rates.The principle applied here uses lines as storing elements and high speed gates as switches. By supplying the data signal as well as the shift and sampling clocks in a serial mode, it is possible to obtain a geometrically linear arrangement of the thick-film circuits so that problems of clock supply and differing signal delays can be excluded. The combination of a few extremely high-speed thick-film circuits with commercial monolithic circuits allows series-to-parallel conversions to be performed in a simple, reliable and flexible way and in any conversion ratio.

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An Integrated Hardware Array for Very High Speed Logic Simulation

VLSI Design ◽

10.1155/1996/13931 ◽

1996 ◽

Vol 4 (2) ◽

pp. 107-118

Author(s):

E. Scott Fehr ◽

Stephen A. Szygenda ◽

Granville E. Ott

Keyword(s):

High Speed ◽

Large Scale ◽

Functional Verification ◽

Logic Simulation ◽

Switching Circuits ◽

Direct Model ◽

Architectural Innovation ◽

Order Of Magnitude ◽

Architectural Principles ◽

Ordered Design

A hardware architecture is proposed which allows direct mapping of design simulation topology onto an acceleration platform. In order to clarify architectural principles, the simulation is confined to functional verification of unit delay, binary valued gate level logic designs. Under this approach, a rank ordered design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, similar to prototyping. Architectural innovation reduces logic complexity and execution time of boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

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