Joint iterative decoding of serially concatenated error control coded CDMA

2001 ◽  
Vol 19 (8) ◽  
pp. 1646-1653 ◽  
Author(s):  
Zhenning Shi ◽  
C. Schlegel
2021 ◽  
Author(s):  
Weilong Dou ◽  
Ming-Min Zhao ◽  
Ming Lei ◽  
Min-Jian Zhao

2016 ◽  
Vol 10 ◽  
pp. 2179-2188 ◽  
Author(s):  
Fouad Ayoub ◽  
Abderrazak Farchane ◽  
Askali Mohamed ◽  
Mostafa Belkasmi ◽  
Mohammed Majid Himmi

2019 ◽  
Vol 2019 ◽  
pp. 1-12 ◽  
Author(s):  
Muhammad Asif ◽  
Wuyang Zhou ◽  
Qingping Yu ◽  
Xingwang Li ◽  
Nauman Ali Khan

This correspondence presents a jointly designed quasicyclic (QC) low-density parity-check (LDPC) coded-relay cooperation with joint-iterative decoding in the destination node. Firstly, a design-theoretic construction of QC-LDPC codes based on a combinatoric design approach known as optical orthogonal codes (OOC) is presented. Proposed OOC-based construction gives three classes of binary QC-LDPC codes with no length-4 cycles by utilizing some known ingredients including binary matrix dispersion of elements of finite field, incidence matrices, and circulant decomposition. Secondly, the proposed OOC-based construction gives an effective method to jointly design length-4 cycles free QC-LDPC codes for coded-relay cooperation, where sum-product algorithm- (SPA-) based joint-iterative decoding is used to decode the corrupted sequences coming from the source or relay nodes in different time frames over constituent Rayleigh fading channels. Based on the theoretical analysis and simulation results, proposed QC-LDPC coded-relay cooperations outperform their competitors under same conditions over the Rayleigh fading channel with additive white Gaussian noise.


2012 ◽  
Vol 241-244 ◽  
pp. 2457-2461 ◽  
Author(s):  
Murali Maheswari ◽  
Gopalakrishnan Seetharaman

In this paper, we present multiple bit error correction coding scheme using extended Hamming product code combined with type II HARQ and keyboard scan based error flipping to correct multiple bit errors for on chip interconnect. The keyboard scan based error flipping reduces the hardware complexity of the decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 86% of reduction in area and 23% of reduction in decoder delay with only small increase in residual flit error rate compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 66% of links power consumption compared to the other error control schemes. The low complexity and excellent residual flit error rate make the proposed code suitable for on chip interconnection links.


2007 ◽  
Vol 16 (6) ◽  
pp. 1557-1567 ◽  
Author(s):  
Marco Grangetto ◽  
Bartolo Scanavino ◽  
Gabriella Olmo ◽  
Sergio Benedetto

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