New discretization scheme for two-dimensional semiconductor device simulation on triangular grid

1998 ◽  
Vol 17 (11) ◽  
pp. 1160-1165 ◽  
Author(s):  
M.B. Patil
Keyword(s):  
Semiconductor Device ◽  
Device Simulation ◽  
Triangular Grid ◽  
Two Dimensional ◽  
Discretization Scheme ◽  
Semiconductor Device Simulation

scholarly journals Topologically Rectangular Grids in the Parallel Simulation of Semiconductor Devices

VLSI Design ◽  
1998 ◽  
Vol 6 (1-4) ◽  
pp. 91-95 ◽  
Author(s):  
A. Asenov ◽  
A. R. Brown ◽  
S. Roy ◽  
J. R. Barker
Keyword(s):  
Simulated Annealing Algorithm ◽  
Semiconductor Device ◽  
Electronic Device ◽  
Device Simulation ◽  
Power Electronic ◽  
Two Dimensional ◽  
Solution Strategy ◽  
Rectangular Grids ◽  
Annealing Algorithm ◽  
2D And 3D

Topologically rectangular grids offer simplicity and efficiency in the design of parallel semiconductor device simulators tailored for mesh connected MIMD platforms. This paper presents several approaches to the generation of topologically rectangular 2D and 3D grids. The effects of the partitioning of such grids on different processor configurations are studied. A simulated annealing algorithm is used to optimise the partitioning of 2D and 3D grids on two dimensional arrays of processors. Problems related to the discretization, parallel matrix generation and solution strategy are discussed. The use of topologically rectangular grids is illustrated through the example of power electronic device simulation.

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