Multi-level logic minimization using implicit don't cares

K.A. Bartlett; R.K. Brayton; G.D. Hachtel; R.M. Jacoby; C.R. Morrison; R.L. Rudell; A. Sangiovanni-Vincentelli; A. Wang

doi:10.1109/43.3211

Multi-level logic minimization using implicit don't cares

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.3211 ◽

1988 ◽

Vol 7 (6) ◽

pp. 723-740 ◽

Cited By ~ 166

Author(s):

K.A. Bartlett ◽

R.K. Brayton ◽

G.D. Hachtel ◽

R.M. Jacoby ◽

C.R. Morrison ◽

...

Keyword(s):

Logic Minimization ◽

Multi Level ◽

Don't Cares

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Multi-Level Logic Minimization based on Multi-Signal Implications

32nd Design Automation Conference ◽

10.1109/dac.1995.250046 ◽

1995 ◽

Cited By ~ 2

Author(s):

Masayuki Yuguchi

Keyword(s):

Logic Minimization ◽

Multi Level

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Efficient SAT-based combinational ATPG using multi-level don't-cares

IEEE International Conference on Test, 2005. ◽

10.1109/test.2005.1584069 ◽

2006 ◽

Cited By ~ 2

Author(s):

N.S. Saluja ◽

S.P. Khatri

Keyword(s):

Multi Level ◽

Don't Cares

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Multi-level logic minimization based on multi-signal implications

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95 ◽

10.1145/217474.217606 ◽

1995 ◽

Cited By ~ 2

Author(s):

Masayuki Yuguchi ◽

Yuichi Nakamura ◽

Kazutoshi Wakabayashi ◽

Tomoyuki Fujita

Keyword(s):

Logic Minimization ◽

Multi Level

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Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers ◽

10.1109/iccad.1991.185332 ◽

2002 ◽

Cited By ~ 16

Author(s):

M. Fujita ◽

Y. Matsunaga

Keyword(s):

Minimal Support ◽

Look Up Table ◽

Logic Minimization ◽

Multi Level

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Multi-level logic minimization through fault dictionary analysis

Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040) ◽

10.1109/iccd.1999.808558 ◽

2003 ◽

Cited By ~ 1

Author(s):

R.W. Mehler ◽

M.R. Mercer

Keyword(s):

Fault Dictionary ◽

Logic Minimization ◽

Multi Level

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Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions

VLSI Design ◽

10.1155/1995/24594 ◽

1995 ◽

Vol 3 (3-4) ◽

pp. 301-313 ◽

Cited By ~ 6

Author(s):

Marek A. Perkowski ◽

Malgorzata Chrzanowska-Jeske ◽

Andisheh Sarabi ◽

Ingo Schäfer

Keyword(s):

Boolean Functions ◽

Logic Synthesis ◽

General Purpose ◽

Compact Representation ◽

Decision Diagrams ◽

Circuit Realization ◽

Orthogonal Expansions ◽

Fine Grain ◽

Multi Level ◽

Don't Cares

This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two families: canonical and non-canonical. While the canonical diagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are also applicable to incompletely specified functions and create don't cares in the process of the creation of the diagram.. They lead to even more compact circuits in logic synthesis and technology mapping.

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