On minimizing the number of L-shaped channels in building-block layout (VLSI)

Y. Cai; D.F. Wong

doi:10.1109/43.229750

On minimizing the number of L-shaped channels in building-block layout (VLSI)

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.229750 ◽

1993 ◽

Vol 12 (6) ◽

pp. 757-769 ◽

Cited By ~ 5

Author(s):

Y. Cai ◽

D.F. Wong

Keyword(s):

Building Block ◽

Building Block Layout

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A timing-driven floorplanning algorithm with the Elmore delay model for building block layout

Integration ◽

10.1016/s0167-9260(98)00016-9 ◽

1999 ◽

Vol 27 (1) ◽

pp. 57-76

Author(s):

Tetsushi Koide ◽

Shin’ichi Wakabayashi

Keyword(s):

Building Block ◽

Delay Model ◽

Building Block Layout

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Three-step pin assignment algorithm for building block layout

Electronics Letters ◽

10.1049/el:19921205 ◽

1992 ◽

Vol 28 (20) ◽

pp. 1882 ◽

Cited By ~ 6

Author(s):

S.-G. Choi ◽

C.-M. Kyung

Keyword(s):

Building Block ◽

Assignment Algorithm ◽

Building Block Layout

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Routing Region Definition and Ordering Scheme for Building-Block Layout

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.1985.1270114 ◽

1985 ◽

Vol 4 (3) ◽

pp. 189-197 ◽

Cited By ~ 17

Author(s):

Wei-Ming Dai ◽

T. Asano ◽

E.S. Kuh

Keyword(s):

Building Block ◽

Building Block Layout

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An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1093/ietfec/e88-a.12.3398 ◽

2005 ◽

Vol E88-A (12) ◽

pp. 3398-3404 ◽

Cited By ~ 1

Author(s):

J. LI

Keyword(s):

Building Block ◽

Layout Design ◽

Tree Representation ◽

Incremental Placement ◽

Placement Algorithm ◽

Building Block Layout

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Branch-and-bound placement for building block layout

Electronics and Communications in Japan (Part III Fundamental Electronic Science) ◽

10.1002/ecjc.4430760702 ◽

1993 ◽

Vol 76 (7) ◽

pp. 15-26 ◽

Cited By ~ 2

Author(s):

Hidetoshi Onodera ◽

Yo Taniguchi ◽

Keikichi Tamaru

Keyword(s):

Branch And Bound ◽

Building Block ◽

Building Block Layout

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Path Delay Analysis for Hierarchical Building Block Layout System

20th Design Automation Conference Proceedings ◽

10.1109/dac.1983.1585684 ◽

1983 ◽

Cited By ~ 19

Author(s):

E. Tamura ◽

K. Ogawa ◽

T. Nakano

Keyword(s):

Building Block ◽

Delay Analysis ◽

Path Delay ◽

Building Block Layout

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Cluster boundary search algorithm for building-block layout optimization

Advances in Engineering Software ◽

10.1016/s0965-9978(98)00056-8 ◽

1998 ◽

Vol 29 (2) ◽

pp. 165-173 ◽

Cited By ~ 11

Author(s):

M.Hasan Imam ◽

Mustahsan Mir

Keyword(s):

Building Block ◽

Search Algorithm ◽

Layout Optimization ◽

Cluster Boundary ◽

Building Block Layout

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Parallel Genetic Algorithm for VLSI Building Block Layout

2006 International Conference on Wireless Communications, Networking and Mobile Computing ◽

10.1109/wicom.2006.170 ◽

2006 ◽

Author(s):

Ning Xu ◽

Feng Huang ◽

Zhonghua Jiang

Keyword(s):

Genetic Algorithm ◽

Building Block ◽

Parallel Genetic Algorithm ◽

Building Block Layout

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Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.1987.1270326 ◽

1987 ◽

Vol 6 (5) ◽

pp. 828-837 ◽

Cited By ~ 32

Author(s):

Wei-Ming Dai ◽

E.S. Kuh

Keyword(s):

Building Block ◽

Global Routing ◽

Floor Planning ◽

Building Block Layout

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Geometric compaction of building-block layout

10.1109/cicc.1989.56778 ◽

1989 ◽

Cited By ~ 5

Author(s):

X.-M. Xiong ◽

E.S. Kuh

Keyword(s):

Building Block ◽

Building Block Layout

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