Performance trade-offs in a parallel test generation/fault simulation environment

S. Patil; P. Banerjee

doi:10.1109/43.103504

Performance trade-offs in a parallel test generation/fault simulation environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.103504 ◽

1991 ◽

Vol 10 (12) ◽

pp. 1542-1558 ◽

Cited By ~ 38

Author(s):

S. Patil ◽

P. Banerjee

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Simulation Environment ◽

Parallel Test ◽

Trade Offs

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Fault partitioning issues in an integrated parallel test generation/fault simulation environment

10.1109/test.1989.82360 ◽

2003 ◽

Cited By ~ 41

Author(s):

S. Patil ◽

P. Banerjee

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Simulation Environment ◽

Parallel Test

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A Cost-Effective FPGA-based Fault Simulation Environment

2011 Workshop on Fault Diagnosis and Tolerance in Cryptography ◽

10.1109/fdtc.2011.19 ◽

2011 ◽

Cited By ~ 6

Author(s):

Angelika Janning ◽

Johann Heyszl ◽

Frederic Stumpf ◽

Georg Sigl

Keyword(s):

Fault Simulation ◽

Cost Effective ◽

Simulation Environment

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Parallel test generation using circuit partitioning and spectral techniques

Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing - PDP '98 - ◽

10.1109/empdp.1998.647208 ◽

2002 ◽

Cited By ~ 6

Author(s):

C. Gil ◽

J. Ortega

Keyword(s):

Test Generation ◽

Circuit Partitioning ◽

Spectral Techniques ◽

Parallel Test

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An optimal design for parallel test generation based on circuit partitioning

Proceedings of 7th International Conference on VLSI Design ◽

10.1109/icvd.1994.282706 ◽

2002 ◽

Cited By ~ 1

Author(s):

Dong Xiang ◽

Dao-Zheng Wei

Keyword(s):

Optimal Design ◽

Test Generation ◽

Circuit Partitioning ◽

Parallel Test

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Functional Test Generation For finite State Machines With Concurrent Fault Simulation

10.1109/atw.1994.747832 ◽

2005 ◽

Author(s):

N.L. Cooray ◽

E.W. Czeck

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Finite State Machines ◽

Functional Test ◽

State Machines ◽

Finite State ◽

Concurrent Fault Simulation

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Fault simulation and test generation

Electronic Design Automation ◽

10.1016/b978-0-12-374364-0.50021-7 ◽

2009 ◽

pp. 851-917

Author(s):

James C.-M. Li ◽

Michael S. Hsiao

Keyword(s):

Test Generation ◽

Fault Simulation

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Behavioral test generation/fault simulation

IEEE Potentials ◽

10.1109/mp.2003.1180938 ◽

2003 ◽

Vol 22 (1) ◽

pp. 27-32 ◽

Cited By ~ 7

Author(s):

Chien-In Henry Chen

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Behavioral Test

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Defect analysis, test generation and fault simulation for gate oxide shorts in CMOS ICs

10.1109/iscas.1990.112567 ◽

2002 ◽

Cited By ~ 10

Author(s):

S.I. Syed ◽

D.M. Wu

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Gate Oxide ◽

Defect Analysis

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A delay fault model for at-speed fault simulation and test generation

2006 IEEE/ACM International Conference on Computer Aided Design ◽

10.1145/1233501.1233521 ◽

2006 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Fault Simulation ◽

Fault Model ◽

Delay Fault

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Portable parallel test generation for sequential circuits

IEEE/ACM International Conference on Computer-Aided Design ◽

10.1109/iccad.1992.279371 ◽

1992 ◽

Cited By ~ 23

Author(s):

Ramkumar ◽

Banerjee

Keyword(s):

Test Generation ◽

Sequential Circuits ◽

Parallel Test

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