ATLAS I: implementing a single-chip ATM switch with backpressure

IEEE Micro ◽  
1999 ◽  
Vol 19 (1) ◽  
pp. 30-41 ◽  
Author(s):  
G. Kornaros ◽  
D. Pnevmatikatos ◽  
P. Vatsolaki ◽  
G. Kalokerinos ◽  
C. Xanthaki ◽  
...  
Keyword(s):  
Single Chip ◽  
Atm Switch

ATLAS I: A single-chip ATM switch for NOWs

1997 ◽  
pp. 88-101 ◽  
Author(s):  
Manolis G. H. Katevenis ◽  
Dimitrios Serpanos ◽  
Panagiota Vatsolaki ◽  
Evangelos Markatos
Keyword(s):  
Single Chip ◽  
Atm Switch

ATLAS I: a single-chip, gigabit ATM switch with HIC/HS links arid multi-lane back-pressure

1998 ◽  
Vol 21 (7-8) ◽  
pp. 481-490 ◽  
Author(s):  
M Katevenis ◽  
D.N Serpanos ◽  
G Dimitriadis
Keyword(s):  
Back Pressure ◽  
Single Chip ◽  
Atm Switch

Low-Dielectric-Constant Materials for ULSI Interlayer-Dielectric Applications

MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho
Keyword(s):  
Packing Density ◽  
Propagation Delay ◽  
Single Chip ◽  
Crosstalk Noise ◽  
Metal Line ◽  
Total Delay ◽  
Interlayer Dielectric ◽  
Low Dielectric ◽  
Interconnect Delay ◽  
Interconnect Technology

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.

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