A flash memory technology with quasi-virtual ground array for low-cost embedded applications

2001 ◽  
Vol 36 (6) ◽  
pp. 969-978 ◽  
Author(s):  
J. Tsouhlarakis ◽  
G. Vanhorebeek ◽  
G. Verhoeven ◽  
J. De Blauwe ◽  
Shiho Kim ◽  
...  
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
Embedded Applications

Understanding and Optimizing Hybrid SSD with High-Density and Low-Cost Flash Memory

2021 ◽  
Author(s):  
Liang Shi ◽  
Longfei Luo ◽  
Yina Lv ◽  
Shicheng Li ◽  
Changlong Li ◽  
...  
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
High Density

scholarly journals Realizing Low-Cost Flash Memory Based Video Caching in Content Delivery Systems

2018 ◽  
Vol 28 (4) ◽  
pp. 984-996 ◽  
Author(s):  
Xuebin Zhang ◽  
Danni Xiong ◽  
Kai Zhao ◽  
Chang Wen Chen ◽  
Tong Zhang
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
Content Delivery ◽  
Delivery Systems ◽  
Video Caching

scholarly journals GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 465 ◽  
Author(s):  
Krzysztof Marcinek ◽  
Witold A. Pleskacz
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
Satellite System ◽  
Microprocessor System ◽  
Instruction Set ◽  
Advantages And Disadvantages ◽  
Wide Range ◽  
Instruction Set Extension ◽  
Baseband Processing ◽  
Global Navigation Satellite

This work presents the results of research toward designing an instruction set extension dedicated to Global Navigation Satellite System (GNSS) baseband processing. The paper describes the state-of-the-art techniques of GNSS receiver implementation. Their advantages and disadvantages are discussed. Against this background, a new versatile instruction set extension for GNSS baseband processing is presented. The authors introduce improved mechanisms for instruction set generation focused on multi-channel processing. The analytical approach used by the authors leads to the introduction of a GNSS-instruction set extension (ISE) for GNSS baseband processing. The developed GNSS-ISE is simulated extensively using PC software and field-programmable gate array (FPGA) emulation. Finally, the developed GNSS-ISE is incorporated into the first-in-the-world, according to the authors’ best knowledge, integrated, multi-frequency, and multi-constellation microcontroller with embedded flash memory. Additionally, this microcontroller may serve as an application processor, which is a unique feature. The presented results show the feasibility of implementing the GNSS-ISE into an embedded microprocessor system and its capability of performing baseband processing. The developed GNSS-ISE can be implemented in a wide range of applications including smart IoT (internet of things) devices or remote sensors, fostering the adaptation of multi-frequency and multi-constellation GNSS receivers to the low-cost consumer mass-market.

Low-cost embedded Flash memory technology

2011 ◽  
Author(s):  
Wein-Town Sun ◽  
Cheng-Jye Liu ◽  
Chun-Yuan Lo ◽  
Yun-Jen Ting ◽  
Ying-Je Chen ◽  
...  
Keyword(s):  
Flash Memory ◽  
Low Cost ◽  
Embedded Flash

An Efficient Flash Translation Layer for Large Block NAND Flash Devices

2015 ◽  
Vol 24 (09) ◽  
pp. 1550138 ◽  
Author(s):  
Tae-Sun Chung ◽  
Dong-Joo Park ◽  
Jongik Kim
Keyword(s):  
Flash Memory ◽  
System Performance ◽  
Smart Phones ◽  
Large Block ◽  
Nand Flash ◽  
Digital Cameras ◽  
Key Factor ◽  
Mp3 Players ◽  
Flash Translation Layer ◽  
Embedded Applications

Recently, flash memory is widely used as a non-volatile storage for embedded applications such as smart phones, MP3 players, digital cameras and so on. The software layer called flash translation layer (FTL) becomes more important since it is a key factor in the overall flash memory system performance. Many researchers have proposed FTL algorithms for small block flash memory in which the size of a physical page of flash memory is equivalent to the size of a data sector of the file system. However, major flash vendors have now produced large block flash memory in which the size of a physical page is larger than the file system's data sector size. Since large block flash memory has new features, designing FTL algorithms specialized to large block flash memory is a challenging issue. In this paper, we provide an efficient FTL named LSTAFF* for large block flash memory. LSTAFF* is designed to achieve better performance by using characteristics of large block flash memory and to provide safety by abiding by restrictions of large block flash memory. Experimental results show that LSTAFF* outperforms existing algorithms on a large block flash memory.

Embedded Processors Nios II-Based LCD Display System Design

2014 ◽  
Vol 513-517 ◽  
pp. 2199-2202 ◽  
Author(s):  
Li Li Tang ◽  
Shao Jun Yao ◽  
Wei Huang ◽  
Jing Wang
Keyword(s):  
Low Cost ◽  
Soft Core ◽  
Embedded Processor ◽  
Interface Circuit ◽  
Hardware Interface ◽  
Development Processes ◽  
Machine Interface ◽  
Software And Hardware ◽  
And Control ◽  
Embedded Applications

Altera's Nios soft core embedded processor, with its low cost, flexible design, etc., has been widely used in embedded applications, while LCD is also increasingly used in a variety of instrumentation and control system as a man-machine interface and display modules. This paper presents a LCD screen of the software and hardware design based on a soft-core Nios embedded processor, introducing hardware interface circuit and software development processes which control the LCD screen, and the corresponding procedures.

scholarly journals An Ultra-Low-Cost Soft Error Protection Scheme Based on the Selection of Critical Variables

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2101
Author(s):  
Yohan Ko
Keyword(s):  
Low Cost ◽  
Soft Error ◽  
Error Protection ◽  
Tolerance Mechanisms ◽  
Protection Scheme ◽  
Systems Software ◽  
Reliability Performance ◽  
Design Cost ◽  
Embedded Applications ◽  
Selection Of

The exponentially increasing occurrence of soft errors makes the optimization of reliability, performance, hardware area, and power consumption one of the main concerns in modern embedded processors. Since the design cost of hardware techniques aimed at improving the reliability of microprocessors is quite expensive for resource-constrained embedded systems, software-level fault tolerance mechanisms have been proposed as an attractive solution for soft error threats. However, many software-level redundancy-based schemes are accompanied by considerable performance overhead, which is not acceptable for many embedded applications. In this work, we have introduced an ultra-low-cost soft error protection scheme for embedded applications, which works based on source-code analysis and identifying critical variables. After identification, these vital variables are adequately protected by placing runtime checks at critical points of execution. Our experimental results based on several applications demonstrate that the proposed scheme can mitigate the failure rate by 47% with negligible performance degradation.

scholarly journals Simple Implementation of a Fuzzy Logic Speed Controller for a PMDC Motor with a Low Cost Arduino Mega

2020 ◽  
Vol 10 (2) ◽  
pp. 5419-5422
Author(s):  
K. S. Belkhir
Keyword(s):  
Fuzzy Logic ◽  
Flash Memory ◽  
Fuzzy Logic Controller ◽  
Low Cost ◽  
Computation Time ◽  
Motor Speed ◽  
Speed Controller ◽  
Simple Implementation ◽  
Speed Mode ◽  
Transient And Steady State

Control of the permanent magnetic direct current PMDC motor is a common practice, hence the importance of the implementation of the PMDC motor speed controller. The results of a fuzzy logic speed controller for the PMDC motor rely on an appropriate base. As the dimension of the rules increases, its difficulty rises which affects computation time and memory requirements. Fuzzy Logic Controller (FLC) can be carried out by a low-cost Arduino Mega which has a small flash memory and a maximum clock speed of 16MHz. It is realized by three membership functions and each was divided into three memberships. The results of the FLC are satisfactory, revealing superior transient and steady-state performance. In addition, the controller is robust to speed mode variations.

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