Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz

2000 ◽  
Vol 35 (4) ◽  
pp. 564-571 ◽  
Author(s):  
K. Ohhata ◽  
F. Arakawa ◽  
T. Kusunoki ◽  
H. Nambu ◽  
K. Kanetani ◽  
...  
Keyword(s):  
Power Reduction ◽  
Operating Frequency ◽  
Access Time ◽  
Reduction Techniques

scholarly journals Comparative analysis of SRAM cell with leakage power reduction approaches

2018 ◽  
Vol 7 (2.7) ◽  
pp. 863
Author(s):  
Damarla Paradhasaradhi ◽  
Kollu Jaya Lakshmi ◽  
Yadavalli Harika ◽  
Busa Ravi Teja Sai ◽  
Golla Jayanth Krishna
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Power Saving ◽  
Vital Role ◽  
Power Reduction ◽  
Leakage Power ◽  
Access Time ◽  
Chip Area ◽  
Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

scholarly journals Power Reduction Techniques for LDPC Decoders

2008 ◽  
Vol 43 (8) ◽  
pp. 1835-1845 ◽  
Author(s):  
Ahmad Darabiha ◽  
Anthony Chan Carusone ◽  
Frank R. Kschischang
Keyword(s):  
Power Reduction ◽  
Reduction Techniques

Computation and power reduction techniques for H.264 intra prediction

2012 ◽  
Vol 36 (3) ◽  
pp. 205-214 ◽  
Author(s):  
Yusuf Adibelli ◽  
Mustafa Parlak ◽  
Ilker Hamzaoglu
Keyword(s):  
Intra Prediction ◽  
Power Reduction ◽  
Reduction Techniques

Power reduction techniques for an 8-core xeon® processor

2009 ◽  
Author(s):  
Stefan Rusu ◽  
Simon Tam ◽  
Harry Muljono ◽  
Jason Stinson ◽  
David Ayers ◽  
...  
Keyword(s):  
Power Reduction ◽  
Reduction Techniques
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