A low-power, high-speed, current-feedback op-amp with a novel Class AB high current output stage

1997 ◽  
Vol 32 (9) ◽  
pp. 1470-1474 ◽  
Author(s):  
J. Bales
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Current ◽  
Output Stage ◽  
Current Feedback ◽  
Current Output ◽  
Class Ab ◽  
Op Amp

Design of a Low-Power Rail-to-Rail CMOS Operational Amplifier

2013 ◽  
Vol 380-384 ◽  
pp. 3304-3307
Author(s):  
Yang Guang ◽  
Bin Yu ◽  
Huang Hai
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Operational Amplifier ◽  
Circuit Simulation ◽  
Open Loop ◽  
Cmos Process ◽  
Output Stage ◽  
Class Ab ◽  
Op Amp ◽  
Rail To Rail

In this paper, an operational amplifier with low-power consumption has been designed. Using the complementary differential pair for the input stage and the class AB structure for the output stage, the common-mode input range and output swing of the proposed circuit could achieved rail-to-rail. Based on TSMC 0.18μm CMOS process, using HSPICE 2008 software for circuit simulation, the results showed that the proposed op-amp has more than 100dB open loop gain, meanwhile the static power consumption is less than 300μw. The circuit's phase margin is 68 degrees, CMRR is 135dB and power supply rejection ratio is 63dB.

Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast
Keyword(s):  
High Performance ◽  
Settling Time ◽  
Cmos Process ◽  
Output Stage ◽  
Common Mode ◽  
Class Ab ◽  
Fully Differential ◽  
Op Amp ◽  
Transconductance Amplifier ◽  
Adaptive Biasing

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

A High Gain Low Power Operational Amplifier using Class AB Output Stage

2019 ◽  
Author(s):  
A. Jeevan Kumar ◽  
K. Lokesh Krishna ◽  
K. Abhinav Viswateja ◽  
K. Gopi ◽  
S. Mohan Rao ◽  
...  
Keyword(s):  
Low Power ◽  
Operational Amplifier ◽  
High Gain ◽  
Output Stage ◽  
Class Ab

IMPROVED LOW-POWER HIGH-SPEED BUFFER AMPLIFIER WITH SLEW-RATE ENHANCEMENT FOR LCD APPLICATIONS

2010 ◽  
Vol 19 (02) ◽  
pp. 325-334 ◽  
Author(s):  
DAVIDE MARANO ◽  
GAETANO PALUMBO ◽  
SALVATORE PENNISI
Keyword(s):  
Low Power ◽  
High Speed ◽  
Liquid Crystal Display ◽  
Slew Rate ◽  
Output Stage ◽  
Line Load ◽  
Rate Enhancement ◽  
Static Operation ◽  
Limited Power ◽  
Buffer Amplifier

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.

Sign in / Sign up

Export Citation Format

Share Document