A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

1996 ◽  
Vol 31 (10) ◽  
pp. 1443-1450 ◽  
Author(s):  
K. Higeta ◽  
M. Usami ◽  
M. Ohayashi ◽  
Y. Fujimura ◽  
M. Nishiyama ◽  
...  
Keyword(s):  
2013 ◽  
Vol 310 ◽  
pp. 494-497
Author(s):  
Xiao Guang Li

Aiming at the problems of the influence in power-supply variations on timing analysis, this paper presents a new method to assign a supply-dependent hold margin based on analysis of scientific data materials, which describe a method to accurately characterize logic gates for the sensitivity of delay on supply-voltage variations, and then the method use a commercial microcontroller as a design example. Experiment results shows that the new method with analysis of scientific materials can get a good performance, even under the existing noise.


2006 ◽  
Vol 527-529 ◽  
pp. 1207-1210 ◽  
Author(s):  
Igor Sankin ◽  
V. Bondarenko ◽  
Robin L. Kelley ◽  
Jeff B. Casady

Wide bandgap semiconductor materials such as SiC or GaN are very attractive for use in high-power, high-temperature, and/or radiation resistant electronics. Monolithic or hybrid integration of a power transistor and control circuitry in a single or multi-chip wide bandgap power semiconductor module is highly desirable for such applications in order to improve the efficiency and reliability. This paper describes a new monolithic SiC JFET IC technology for high-temperature smart power applications that allows for on-chip integration of control circuitry and normally-off power switch. In order to demonstrate the feasibility of this technology, hybrid logic gates with maximum switching frequency > 20 MHz and normally-off 900 V power switch have been fabricated on alumina substrates using discrete enhanced and depletion mode vertical trench JFETs.


Author(s):  
Khanh N. Dang ◽  
Michael Meyer ◽  
Yuichi Okuyama ◽  
Abderazek Ben Abdallah ◽  
Xuan-Tu Tran

Nanophotonics ◽  
2017 ◽  
Vol 6 (1) ◽  
pp. 365-376 ◽  
Author(s):  
Xiaoyu Yang ◽  
Xiaoyong Hu ◽  
Hong Yang ◽  
Qihuang Gong

AbstractIn this study, nanoscale integrated all-optical XNOR, XOR, and NAND logic gates were realized based on all-optical tunable on-chip plasmon-induced transparency in plasmonic circuits. A large nonlinear enhancement was achieved with an organic composite cover layer based on the resonant excitation-enhancing nonlinearity effect, slow light effect, and field confinement effect provided by the plasmonic nanocavity mode, which ensured a low excitation power of 200 μW that is three orders of magnitude lower than the values in previous reports. A feature size below 600 nm was achieved, which is a one order of magnitude lower compared to previous reports. The contrast ratio between the output logic states “1” and “0” reached 29 dB, which is among the highest values reported to date. Our results not only provide an on-chip platform for the study of nonlinear and quantum optics but also open up the possibility for the realization of nanophotonic processing chips based on nonlinear plasmonics.


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