Top-down pass-transistor logic design

K. Yano; Y. Sasaki; K. Rikino; K. Seki

doi:10.1109/4.509865

Top-down pass-transistor logic design

IEEE Journal of Solid-State Circuits ◽

10.1109/4.509865 ◽

1996 ◽

Vol 31 (6) ◽

pp. 792-803 ◽

Cited By ~ 155

Author(s):

K. Yano ◽

Y. Sasaki ◽

K. Rikino ◽

K. Seki

Keyword(s):

Logic Design ◽

Top Down ◽

Pass Transistor ◽

Pass Transistor Logic

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Top-down logic design with pass-transistor cells and efficient synthesiser

Electronics Letters ◽

10.1049/el:19980880 ◽

1998 ◽

Vol 34 (12) ◽

pp. 1180 ◽

Cited By ~ 1

Author(s):

Shen-Fu Hsiao ◽

Jia-Siang Yeh

Keyword(s):

Logic Design ◽

Top Down ◽

Pass Transistor

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CMOS differential pass-transistor logic design

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.1987.1052705 ◽

1987 ◽

Vol 22 (2) ◽

pp. 216-222 ◽

Cited By ~ 32

Author(s):

J.H. Pasternak ◽

A.S. Shubat ◽

C.A.T. Salama

Keyword(s):

Logic Design ◽

Pass Transistor ◽

Pass Transistor Logic

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Dual-threshold pass-transistor logic design

Proceedings of the 19th ACM Great Lakes symposium on VLSI - GLSVLSI '09 ◽

10.1145/1531542.1531610 ◽

2009 ◽

Cited By ~ 1

Author(s):

Lara D. Oliver ◽

Krishnendu Chakrabarty ◽

Hisham Z. Massoud

Keyword(s):

Logic Design ◽

Pass Transistor ◽

Pass Transistor Logic

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Pass-transistor logic design

International Journal of Electronics ◽

10.1080/00207219108921324 ◽

1991 ◽

Vol 70 (4) ◽

pp. 739-749 ◽

Cited By ~ 26

Author(s):

WALEED AL-ASSADI ◽

ANURA P. JAYASUMANA ◽

YASHWANT K. MALAIYA

Keyword(s):

Logic Design ◽

Pass Transistor ◽

Pass Transistor Logic

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A high signal swing pass-transistor logic using surrounding gate transistor

2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502) ◽

10.1109/sispad.2000.871261 ◽

2002 ◽

Cited By ~ 1

Author(s):

T. Endoh ◽

T. Funaki ◽

H. Sakuraba ◽

F. Masuoka

Keyword(s):

High Signal ◽

Surrounding Gate ◽

Pass Transistor ◽

Pass Transistor Logic ◽

Signal Swing

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CMOS differential pass-transistor logic (CMOS DPTL) predischarge buffer design

Thirteenth National Radio Science Conference. NRSC '96 ◽

10.1109/nrsc.1996.551142 ◽

2002 ◽

Author(s):

S.I. Kayed ◽

H.F. Ragaei

Keyword(s):

Buffer Design ◽

Pass Transistor ◽

Pass Transistor Logic

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A 1.5 ns 32 b CMOS ALU in double pass-transistor logic

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers ◽

10.1109/isscc.1993.280071 ◽

1993 ◽

Cited By ~ 49

Author(s):

M. Suzuki ◽

N. Ohkubo ◽

T. Yamanaka ◽

A. Shimizu ◽

K. Sasaki

Keyword(s):

Double Pass ◽

Pass Transistor ◽

Pass Transistor Logic

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Digital compressor structure in neural network implementation using complex complementary pass-transistor logic (C/sup 2/PL)

Proceedings of 1994 37th Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.1994.519282 ◽

2002 ◽

Author(s):

D. Zhang ◽

M. Kamel ◽

M.I. Elmasry

Keyword(s):

Neural Network ◽

Pass Transistor ◽

Pass Transistor Logic

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Novel CMOS static ternary logic using double pass-transistor logic

The 2nd International Conference on Information Science and Engineering ◽

10.1109/icise.2010.5689867 ◽

2010 ◽

Cited By ~ 5

Author(s):

Guoqiang Hang ◽

Xuanchang Zhou

Keyword(s):

Ternary Logic ◽

Double Pass ◽

Pass Transistor ◽

Pass Transistor Logic

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Power Efficient Pulse Triggered Flip-Flop Design Using Pass Transistor Logic

Emerging Trends in Computing and Expert Technology - Lecture Notes on Data Engineering and Communications Technologies ◽

10.1007/978-3-030-32150-5_5 ◽

2019 ◽

pp. 48-61

Author(s):

C. S. Manju ◽

N. Poovizhi ◽

R. Rajkumar

Keyword(s):

Flip Flop ◽

Power Efficient ◽

Pass Transistor ◽

Pass Transistor Logic

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