A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces

Dao-Long Chen

doi:10.1109/4.508265

A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces

IEEE Journal of Solid-State Circuits ◽

10.1109/4.508265 ◽

1996 ◽

Vol 31 (8) ◽

pp. 1170-1176 ◽

Cited By ~ 10

Author(s):

Dao-Long Chen

Keyword(s):

High Speed ◽

Data Recovery ◽

Clock Data Recovery ◽

Area Efficient

Download Full-text

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery

2010 IEEE International Test Conference ◽

10.1109/test.2010.5699242 ◽

2010 ◽

Cited By ~ 1

Author(s):

Sudeep Puligundla ◽

Fulvio Spagna ◽

Lidong Chen ◽

Amanda Tran

Keyword(s):

High Speed ◽

Data Recovery ◽

Adaptive Equalization ◽

Serial Link ◽

Baud Rate ◽

Clock Data Recovery

Download Full-text

Multi-rate Clock-Data recovery solution in high speed serial links

2015 IEEE 35th International Conference on Electronics and Nanotechnology (ELNANO) ◽

10.1109/elnano.2015.7146883 ◽

2015 ◽

Author(s):

Melikyan Vazgen ◽

Sahakyan Arthur ◽

Shishmanyan Aram ◽

Hekimyan Arsen

Keyword(s):

High Speed ◽

Data Recovery ◽

Serial Links ◽

Clock Data Recovery

Download Full-text

Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor

2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2018.8623900 ◽

2018 ◽

Author(s):

Gyunam Jeon ◽

Yong-Bin Kim

Keyword(s):

Data Recovery ◽

Clock Data Recovery ◽

Phase Interpolator ◽

Area Efficient

Download Full-text

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2019.2944791 ◽

2020 ◽

Vol 67 (5) ◽

pp. 1438-1446 ◽

Cited By ~ 1

Author(s):

Stefan Biereigel ◽

Szymon Kulis ◽

Pedro Leitao ◽

Rui Francisco ◽

Paulo Moreira ◽

...

Keyword(s):

High Speed ◽

Fault Tolerant ◽

Low Noise ◽

Data Recovery ◽

Feed Forward ◽

Clock Data Recovery ◽

Radiation Hardened

Download Full-text

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS

2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) ◽

10.1109/lascas.2019.8667542 ◽

2019 ◽

Cited By ~ 2

Author(s):

Jeffrey Prinzie ◽

Szymon Kulis ◽

Pedro Leitao ◽

Rui Francisco ◽

Valentijn De Smedt ◽

...

Keyword(s):

High Speed ◽

Fault Tolerant ◽

Low Noise ◽

Data Recovery ◽

Feed Forward ◽

Clock Data Recovery ◽

Radiation Hardened

Download Full-text

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

Area Efficient

Download Full-text

Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2019.8754423 ◽

2019 ◽

Author(s):

Diptesh Datta ◽

Piyush Dewangan ◽

Neelam Surana ◽

Joycee Mekie

Keyword(s):

High Speed ◽

Content Addressable Memory ◽

Ternary Content Addressable Memory ◽

Area Efficient

Download Full-text

Design of high-speed burst mode clock and data recovery IC for passive optical network

10.1117/12.628728 ◽

2005 ◽

Author(s):

Minhui Yan ◽

Xiaobin Hong ◽

Wei-Ping Huang ◽

Jin Hong

Keyword(s):

High Speed ◽

Optical Network ◽

Clock And Data Recovery ◽

Data Recovery ◽

Passive Optical Network ◽

Burst Mode

Download Full-text

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Materials Today Proceedings ◽

10.1016/j.matpr.2020.07.677 ◽

2020 ◽

Author(s):

A. Arunkumar Gudivada ◽

K. Jayaram Kumar ◽

Srinivasa Rao Jajula ◽

Durga Prasad Siddani ◽

Praveen Kumar Poola ◽

...

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

High Speed ◽

Quantum Dot Cellular Automata ◽

Wallace Tree ◽

Wallace Tree Multiplier ◽

Area Efficient

Download Full-text

High-speed area-efficient recursive DFT/IDFT architectures

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) ◽

10.1109/iscas.2004.1328757 ◽

2004 ◽

Author(s):

Lan-Da Van ◽

Chih-Chyau Yang

Keyword(s):

High Speed ◽

Area Efficient

Download Full-text

A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces

Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery

Multi-rate Clock-Data recovery solution in high speed serial links

Area Efficient 4Gb/s Clock Data Recovery Using Improved Phase Interpolator with Error Monitor

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search

Design of high-speed burst mode clock and data recovery IC for passive optical network

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

High-speed area-efficient recursive DFT/IDFT architectures

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata