A monolithic 2.3-Gb/s 100-mW clock and data recovery circuit in silicon bipolar technology

1993 ◽  
Vol 28 (12) ◽  
pp. 1310-1313 ◽  
Author(s):  
M. Soyuer
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Bipolar Technology ◽  
S 100 ◽  
Silicon Bipolar Technology

Monolithic 2.5-Gb/s clock and data recovery circuit based on silicon bipolar technology

1998 ◽  
Author(s):  
Andrea Pallotta ◽  
Francesco Centurelli ◽  
Francesco Loriga ◽  
Alessandro Trifiletti
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Bipolar Technology ◽  
Silicon Bipolar Technology

A 40-Gb/s integrated clock and data recovery circuit in a 50-GHz f/sub T/ silicon bipolar technology

1999 ◽  
Vol 34 (9) ◽  
pp. 1320-1324 ◽  
Author(s):  
M. Wurzer ◽  
J. Bock ◽  
H. Knapp ◽  
W. Zirwas ◽  
F. Schumann ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Data Recovery ◽  
Bipolar Technology ◽  
Silicon Bipolar Technology

Erratum: 24 Gbit/s regenerating demultiplexer IC in silicon bipolar technology

1991 ◽  
Vol 27 (9) ◽  
pp. 787
Author(s):  
J. Hauenschild ◽  
H.-M. Rein ◽  
W. McFarland ◽  
D. Pettengill
Keyword(s):  
Bipolar Technology ◽  
Silicon Bipolar Technology

scholarly journals A Gated Oscillator Clock and Data Recovery Circuit for Nanowatt Wake-Up and Data Receivers

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 780
Author(s):  
Matteo D’Addato ◽  
Alessia M. Elgani ◽  
Luca Perilli ◽  
Eleonora Franchi Scarselli ◽  
Antonio Gnudi ◽  
...  
Keyword(s):  
Data Streams ◽  
Clock And Data Recovery ◽  
Data Recovery ◽  
Rf Power ◽  
Input Matching ◽  
Analog Front End ◽  
Frequency Mismatch ◽  
Free Running ◽  
Frequency Calibration ◽  
Total Sensitivity

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (Nm). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to Nm = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10−3 missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the Nm ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

A 5-Gbit/s Clock- and Data-Recovery Circuit With 1/8-Rate Linear Phase Detector in 0.18-${\rm \mu}\hbox{m}$ CMOS Technology

2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Linear Phase
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