FPGA implementation of the LRU algorithm for video compression

The proposed work is a modern hardware based architecture for performing transformation, quantisation and prediction is designed which is used for H.264/AVC video standards. This designed hardware find its importance in advanced H264 encoders which are repeatedly find its application in HDTV applications. The H264/AV Codec does video compression and video decompression for prospect broadband and wireless networks. A low complexity discrete cosine transform is used by DSP embedded multiplier. An intra-prediction equation are employed to get low latency, high throughput, efficient utilization of resources. The proposed architecture also employs both pipeline & parallel process methods. The proposed architecture is implemented using VHDL and synthesised for Virtex 5, and the device is 5vlx50tff665.

Download Full-text

FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression

Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays - FPGA '01 ◽

10.1145/360276.360358 ◽

2001 ◽

Cited By ~ 5

Author(s):

S. Ramachandran ◽

S. Srinivasan

Keyword(s):

Motion Estimation ◽

Real Time ◽

Video Compression ◽

Estimation Algorithm ◽

Fpga Implementation ◽

Fast Motion Estimation ◽

Fast Motion ◽

Motion Estimation Algorithm

Download Full-text

FPGA Implementation of the LRU Algorithm for Video Compression

IEEE International Conference on Consumer Electronics ◽

10.1109/icce.1994.582158 ◽

1994 ◽

Cited By ~ 1

Author(s):

O. Fatemi ◽

F. Idris ◽

S. Panchanathan

Keyword(s):

Video Compression ◽

Fpga Implementation

Download Full-text

Low Power FPGA Implementation of Multi-View Video Coding with Hybrid Compression and Decompression Algorithm

International Journal of Engineering and Advanced Technology - Regular Issue ◽

10.35940/ijeat.c5495.029320 ◽

2020 ◽

Vol 9 (3) ◽

pp. 2395-2403

Keyword(s):

Video Coding ◽

Video Compression ◽

Hybrid Algorithm ◽

Research Work ◽

Fpga Implementation ◽

Computational Time ◽

Discrete Wavelet ◽

Compression Process ◽

Compression Technique ◽

Flip Flop

The video is one of the most useful and most appealing medium to represent some information. More usage of digital multi-media via communications media, wireless communications, intranet, internet and cellular mobile leads to the uncontrollable growth of data in media. The video compression technique is used in this research work to improve the processing speed of the entire system. In this work, Low Cost - Multi Video Coding - Hybrid Compression and Decompression (LC-MVC-HCD) method is used to reduce computation complexity. The combinational of Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT) algorithms are denoted as hybrid algorithm. Based on this hybrid algorithm, the compression process is performing which improves the video coding efficiency of MVC. The LC-MVC-HCD methodwas implemented in the Matlab, Xilinx and Cadence tool. In Application Specific Integrated Circuit (ASIC) implementation, the area, power, and delay minimized by using the cadence encounter tool with 180nm and 45nm technology. In Field Programmable Gate Array (FPGA) implementation, the number of Lookup Tables (LUTs), slice, and flip-flop are minimized based on two different kinds of Virtex devices such as Virtex -6 and Virtex-7. In Matlab, Peak Signal to Noise Ratio (PSNR), computational time and bit error rate were analyzed for the LC-MVC-HCD method. The experimental outcome showed that the proposed methodology has improved performance ASIC and FPGA up to 2-3% compared to existing methods like Direct mode decision MVC and LC-MVC-DWT.

Download Full-text